Block Diagram - Hitachi SH7032 Hardware Manual

8.1.2

Block Diagram

Figure 8.1 shows a block diagram of the bus state controller.
WAIT
WRH, WRL
HBS, LBS
CS7 to CS0
CASH, CASL
RAS
CMI interrupt request
DPH, DPL
PEI interrupt request
Interrupt
controller
WCR: Wait state control register
BCR: Bus control register
DCR: DRAM area control register
RCR: Refresh control register
102
Wait control
unit
RD
Area control
unit
AH
DRAM
control
unit
Parity control
unit
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
PCR: Parity control register
Figure 8.1 Block Diagram of BSC
Bus
interface
WCR1
WCR2
WCR3
BCR
DCR
RCR
RTCSR
RTCNT
Comparator
RTCOR
PCR
BSC