Next Data Register B (Ndrb) - Hitachi SH7032 Hardware Manual

Bit:
Bit name:
Initial value:
R/W:
11.2.4

Next Data Register B (NDRB)

NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3
and 2 (TP15–TP8). When used for TPC output, the contents of NDRB are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register, TPCR, occurs.
The address of NDRB differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 3 and 2. NDRB is initialized to H'00 by a reset. It is not
initialized in standby mode.
Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by
the same compare match, the address of NDRB is H'FFFFF4. The upper 4 bits become group 3
and the lower 4 bits become group 2. Address H'5FFFFF6 consists entirely of reserved bits. These
bits are always read as 1, and the write value should always be 1.
Address H'5FFFFF4:
• Bits 7–4 (Next Data 15–12 (NDR15–NDR12)): NDR15–NDR12 store the next output data for
TPC output group 3.
• Bits 3–0 (Next Data 11–8 (NDR11–NDR8)): NDR11–NDR8 store the next output data for
TPC output group 2.
Bit:
Bit name:
Initial value:
R/W:
Address H'5FFFFF6:
• Bits 7–0 (Reserved): These bits are always read as 1. The write value should always be 1.
316
7 6
— —
1 1
— —
7 6
NDR15 NDR14 NDR13
0 0
R/W R/W
5 4
— — NDR3
1 1
— — R/W
5 4
NDR12 NDR11
0 0
R/W R/W R/W
3 2 1
NDR2 NDR1
0 0 0
R/W R/W
3 2 1
NDR10 NDR9
0 0 0
R/W R/W
0
NDR0
0
R/W
0
NDR8
0
R/W