Hitachi SH7032 Hardware Manual page 57

Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory, data is loaded into to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption
during branching is reduced by first executing the instruction that follows the branch instruction,
and then branching. See the SH-1/SH-2 Programming Manual for details.
Table 2.3 Delayed Branch Instructions
SH7000 Series CPU
BRA TRGET
ADD R1,R0
Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip
multiplier enable 16-bit × 16-bit → 32-bit multiplication operations to be executed in 1–3 cycles.
16-bit × 16-bit + 42-bit → 42-bit multiplication/accumulation operations can be executed in 2–3
cycles.
T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the
condition (True/False) that determines if the program will branch. The T bit in the status register is
only changed by selected instructions, thus improving the processing speed.
Table 2.4 T Bit
SH7000 Series CPU
CMP/GE R1,R0
BT TRGET0
BF TRGET1
ADD #–1,R0
TST R0,R0
BT TRGET
Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or
longword immediate data is not located in instruction codes but is stored in a memory table. The
memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative
addressing mode with displacement.
22
Description
Executes an ADD before
branching to TRGET.
Description
T bit is set when R0 ≥ R1. The program
branches to TRGET0 when R0 ≥ R1
and to TRGET1 when R0<R1.
T bit is not changed by ADD. T bit is set
when R0 = 0. The program branches if
R0 = 0.
Conventional CPU
ADD.W R1,R0
BRA TRGET
Conventional CPU
CMP.W R1,R0
BGE TRGET0
BLT TRGET1
SUB.W #1,R0
BEQ TRGET