Timer Mode Register (Tmdr) - Hitachi SH7032 Hardware Manual

• Bit 1 (Timer Synchro 1 (SYNC1)): SYNC1 selects synchronizing mode for channel 1.
Bit 1: SYNC1
0
1
• Bit 0 (Timer Synchro 0 (SYNC0)): SYNC0 selects synchronizing mode for channel 0.
Bit 0: SYNC0
0
1
10.2.3

Timer Mode Register (TMDR)

The timer mode register (TMDR) is an eight-bit read/write register that selects PWM mode for
channels 0–4, sets phase counting mode for channel 2, and sets the conditions for the overflow
flag (OVF). TMDR is initialized to H'80 or H'00 by a reset and in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Undefined
• Bit 7 (Reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
• Bit 6 (Phase Counting Mode (MDF)): MDF selects phase counting mode for channel 2.
Bit 6: MDF
0
1
Description
The timer counter for channel 1 (TCNT1) operates independently
(Preset/clear of TCNT1 is independent of other channels) (Initial value)
Channel 1 operates synchronously. Synchronized preset/clear of
TNCT1 enabled.
Description
The timer counter for channel 0 (TCNT0) operates independently
(Preset/clear of TCNT0 is independent of other channels)
Channel 0 operates synchronously. Synchronized preset/clear of
TNCT0 enabled.
7 6 5
— MDF FDIR
0 0
*
— R/W R/W
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
4 3
PWM4 PWM3 PWM2
0 0
R/W R/W
(Initial value)
2 1
PWM1 PWM0
0 0
R/W R/W R/W
(Initial value)
0
0
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