Hitachi SH7032 Hardware Manual page 208

The maximum number of states from BREQ input to bus release are used when B is a cycle
comprising the maximum number of states for which the bus is not released; the number of states
is the maximum number of states for which bus is not released + approx. 4.5 states.
The maximum number of states for which the bus is not released requires careful investigation.
Bus cycle
BREQ
BACK
Figure 8.43 When BREQ is Input without Satisfying tBRQS
1. Cycles in which bus is not released
(a) One bus cycle
The bus is never released during one bus cycle. For example, in the case of a longword
read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit
ordinary space, as shown in figure 8.44. The bus is not released between these accesses.
Assuming one memory access to require 2 states, the bus is not released for a period of 8
states.
(b) TAS instruction read cycle and write cycle
The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45).
The TAS instruction read cycle and write cycle should be regarded as one bus cycle during
which the bus is not released.
Figure 8.45 TAS Instruction Read Cycle and Write Cycle
CK
A
tBRQS
8 bits 8 bits
Cycle during which
bus is not released
Figure 8.44 One Bus Cycle
Read cycle
Cycle during which bus is
not released (1 bus cycle)
B
tBACD1
8 bits 8 bits
Write cycle
Bus release
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