Interrupt Priority Setting Register D (Iprd) Intc - Hitachi SH7032 Hardware Manual

Superh risc engine
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A.2.32
Interrupt Priority Setting Register D (IPRD)
• Start Address: H'5FFFF8A
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.33 IPRD Bit Functions
Bit
Bit name
15–12
(Set ITU2 priority level)
11–8
(Set ITU3 priority level)
7–4
(Set ITU4 priority level)
3–0
(Set SCI0 priority level)
598
15
14
13
0
0
R/W
R/W
R/W
7
6
0
0
R/W
R/W
R/W
12
11
0
0
0
R/W
R/W
5
4
3
0
0
0
R/W
R/W
Description
Sets the ITU2 priority level value
Sets the ITU3 priority level value
Sets the ITU4 priority level value
Sets the SCI0 priority level value
INTC
10
9
0
0
R/W
R/W
R/W
2
1
0
0
R/W
R/W
R/W
8
0
0
0

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