Block Diagram; Timers - Hitachi SH7032 Hardware Manual

1.2

Block Diagram

RES
WDTOVF
MD2
MD1
MD0
NMI
CK
EXTAL
XTAL
*2
V (V )
CC PP
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
AV
ref
AV
CC
AV
SS
: Peripheral address bus (24 bits)
: Peripheral data bus (16 bits)
: Internal address bus (24 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
Notes: *1 The SH7032 has 8 kB of RAM and no PROM or masked ROM. The SH7034 has 4 kB
of RAM and 64 kB of PROM or masked ROM.
*2 V : SH7034 (PROM version)
PP
8
Port A
PROM or
*1
masked ROM
CPU
User
Interrupt
break
controller
controller
Serial communi-
cation interface
(2 channels)
Programmable
timing pattern
controller
Port C
Figure 1.1 Block Diagram
Address
*1
RAM
Direct
memory
access
controller
Bus state controller
16-bit
integrated timer
pulse unit
A/D
Watchdog
converter
timer
Port B
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (HBS)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0