Table 10.21 ITU Operating Modes (Channel 3)
TSNC
Operating
Mode
Sync
MDF FDIR PWM
Synch-
SYNC3
—
ronized
= 1
preset
√
PWM
—
mode
√
Output
—
compare A
function
√
Output
—
compare B
function
√
Input
—
capture A
function
√
Input
—
capture B
function
Counter Clear Function
√
Clear at
—
compare
match/
input
capture A
√
Clear at
—
compare
match/
input
capture B
Synch-
SYNC3
—
ronized
= 1
clear
304
TMDR
TFCR
Reset
Comp
Sync
PWM
PWM Buffer
√
√ *
√
2
—
—
PWM3
CMD1
CMD1
= 1
= 0
= 0
—
PWM3
CMD1
CMD1
= 0
= 0
= 0
√
—
CMD1
CMD1
= 0
= 0
—
PWM3
CMD1
CMD1
= 0
= 0
= 0
—
PWM3
CMD1
CMD1
= 0
= 0
= 0
√
√ *
—
CMD1
= 1,
CMD0
= 0
inhib-
ited
√
—
CMD1
CMD1
= 0
= 0
√
√
—
CMD1
= 1,
CMD0
= 0
inhib-
ited
Register Setting
TOCR
Output
Level
Select IOA
√
√
—
√
—
—
√
—
IOA2 = 0,
others:
don't care
√
√
—
√
—
IOA2 = 1,
others:
don't care
√
√
—
√
√
3
—
√
√
—
√
√
—
TIOR3
TCR3
Clear
IOB
Select
√
√
√ *
√
1
√
√
√
IOB2 = 0,
others:
don't care
√
√
√
IOB2 = 1,
others:
don't care
√
CCLR1
= 0
CCLR0
= 1
√
CCLR1
= 1
CCLR0
= 0
√
CCLR1
= 1
CCLR0
= 1
Clock
Select
√
√
√
√
√
√
√
√
√