Dma Operation Registers (Dmaor) Dmac - Hitachi SH7032 Hardware Manual

A.2.28 DMA Operation Registers (DMAOR)
• Start Address: H'5FFFF48
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written, to clear the flag.
Table A.29 DMAOR Bit Functions
Bit Bit name
9,8 Priority mode bits 1, 0
(PR1,PR0)
2 Address error flag bit
(AE)
1 NMI flag bit (NMIF)
0 DMA master enable
bit (DME)
594
15 14 13
— — —
0 0 0
— — —
7 6 5
— — —
0 0 0
— — —
Value Description
0 0 Priority order is fixed
(Channel 0 > channel 3 > channel 2 > channel 1)
0 1 Priority order is fixed (Channel 1 > channel 3 > channel 2 >
channel 0)
1 0 Round-robin priority order (Immediately after reset:
Channel 0 > channel 3 > channel 2 > channel 1)
1 1 External-pin-alternating mode priority order (Immediately
after reset: Channel 3 > channel 2 > channel 1 > channel
0)
0 No errors caused by DMAC
Clear Condition: Write 0 in AE after reading AE
1 Address error caused by DMAC
0 No NMI interrupt
Clear Condition: Write 0 in NMIF after reading NMIF
1 NMI interrupt generated
0 DMA transfer disabled for all channels
1 DMA transfer enabled for all channels
12 11 10
— — —
0 0 0
— — —
4 3 2
— — AE
0 0 0
R/(W) *
— —
DMAC
9 8
PR1 PR0
0 0
R/W R/W
1 0
NMIF DME
0 0
R/(W) *
R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)