Status Flag Clear Timing - Hitachi SH7032 Hardware Manual

10.5.2

Status Flag Clear Timing

The status flags are cleared by being read by the CPU when set to 1, then being written with 0.
This timing is shown in figure 10.57.
TSR write cycle
T1 T2 T3
CK
TSR address
Address
IMF, OVF
Figure 10.57 Timing of Status Flag Clearing
288