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Hitachi SH7709S Hardware Manual

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Summary of Contents for Hitachi SH7709S

Page 1 DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark,...
Page 2 Hitachi SuperH™ RISC engine SH7709S Hardware Manual ADE-602-250 Rev. 1.0 09/21/01 Hitachi, Ltd.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.hitachi.co.jp/Sicd/English/Products/micome.htm • User manuals for SH7709S Name of Document Document No. SH7709S Series Hardware Manual...
Page 5 • User manuals for development tools Name of Document Document No. C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Hitachi Embedded Workshop User’s Manual ADE-702-201 • Application note Name of Document Document No. C/C++ Compiler Guide ADE-xxx-xxx...
Page 6: Table Of Contents
Memory Management Unit (MMU) ............57 Overview ..........................57 3.1.1 Features ......................... 57 3.1.2 Role of MMU......................57 3.1.3 SH7709S MMU ....................60 3.1.4 Register Configuration ..................65 Register Description ......................65 TLB Functions........................67 3.3.1 Configuration of the TLB..................67 3.3.2 TLB Indexing ......................
Page 7 MMU Functions ......................... 73 3.4.1 MMU Hardware Management ................73 3.4.2 MMU Software Management................73 3.4.3 MMU Instruction (LDTLB).................. 74 3.4.4 Avoiding Synonym Problems ................76 MMU Exceptions ....................... 78 3.5.1 TLB Miss Exception ..................... 78 3.5.2 TLB Protection Violation Exception ..............79 3.5.3 TLB Invalid Exception..................
Page 8 5.1.3 Register Configuration ..................109 Register Description ......................109 5.2.1 Cache Control Register (CCR)................109 5.2.2 Cache Control Register 2 (CCR2) ................ 110 Cache Operation ......................... 113 5.3.1 Searching the Cache....................113 5.3.2 Read Access ......................115 5.3.3 Prefetch Operation ....................115 5.3.4 Write Access ......................
Page 9 Section 7 User Break Controller ..................153 Overview ..........................153 7.1.1 Features ......................... 153 7.1.2 Block Diagram ...................... 154 7.1.3 Register Configuration ..................155 Register Descriptions......................156 7.2.1 Break Address Register A (BARA) ..............156 7.2.2 Break Address Mask Register A (BAMRA)............157 7.2.3 Break Bus Cycle Register A (BBRA) ..............
Page 10 8.4.2 Canceling Standby Mode ..................193 8.4.3 Clock Pause Function.................... 194 Module Standby Function ....................195 8.5.1 Transition to Module Standby Function..............195 8.5.2 Clearing Module Standby Function ..............195 Timing of STATUS Pin Changes..................196 8.6.1 Timing for Resets....................196 8.6.2 Timing for Canceling Standby ................
Page 11 10.1.1 Features ......................... 227 10.1.2 Block Diagram ...................... 229 10.1.3 Pin Configuration ....................230 10.1.4 Register Configuration ..................232 10.1.5 Area Overview ...................... 233 10.1.6 PCMCIA Support....................236 10.2 BSC Registers ........................239 10.2.1 Bus Control Register 1 (BCR1) ................239 10.2.2 Bus Control Register 2 (BCR2) ................
Page 12 11.1.3 Pin Configuration ....................334 11.1.4 Register Configuration ..................335 11.2 Register Descriptions......................337 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ........... 337 11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) ........338 11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......339 11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........
Page 13 12.3.2 Input Capture Function..................407 12.4 Interrupts ..........................408 12.4.1 Status Flag Setting Timing..................408 12.4.2 Status Flag Clearing Timing ................. 409 12.4.3 Interrupt Sources and Priorities................409 12.5 Usage Notes........................410 12.5.1 Writing to Registers ....................410 12.5.2 Reading Registers....................410 Section 13 Realtime Clock (RTC) ...................
Page 14 14.1 Overview ..........................431 14.1.1 Features ......................... 431 14.1.2 Block Diagram ...................... 432 14.1.3 Pin Configuration ....................435 14.1.4 Register Configuration ..................436 14.2 Register Descriptions......................436 14.2.1 Receive Shift Register (SCRSR)................436 14.2.2 Receive Data Register (SCRDR) ................437 14.2.3 Transmit Shift Register (SCTSR) .................
Page 15 Section 16 Serial Communication Interface with FIFO (SCIF) ......515 16.1 Overview ..........................515 16.1.1 Features ......................... 515 16.1.2 Block Diagram ...................... 516 16.1.3 Pin Configuration ....................519 16.1.4 Register Configuration ..................520 16.2 Register Descriptions......................521 16.2.1 Receive Shift Register (SCRSR)................521 16.2.2 Receive FIFO Data Register (SCFRDR) ..............
Page 16 18.3.4 Port D Control Register (PDCR) ................577 18.3.5 Port E Control Register (PECR)................578 18.3.6 Port F Control Register (PFCR)................579 18.3.7 Port G Control Register (PGCR) ................580 18.3.8 Port H Control Register (PHCR)................581 18.3.9 Port J Control Register (PJCR) ................583 18.3.10 Port K Control Register (PKCR) ................
Page 17 21.1.4 Register Configuration ..................640 21.2 Register Descriptions......................641 21.2.1 D/A Data Registers 0 and 1 (DADR0/1) .............. 641 21.2.2 D/A Control Register (DACR)................641 21.3 Operation ..........................643 Section 22 Hitachi User Debugging Interface (H-UDI) ..........645 22.1 Overview ..........................645...
Page 18 22.2 Hitachi User Debugging Interface (H-UDI)............... 645 22.2.1 Pin Descriptions ....................645 22.2.2 Block Diagram ...................... 646 22.3 Register Descriptions......................646 22.3.1 Bypass Register (SDBPR) ..................647 22.3.2 Instruction Register (SDIR) .................. 647 22.3.3 Boundary Scan Register (SDBSR)................ 648 22.4 H-UDI Operation........................ 655 22.4.1 TAP Controller......................
Page 19 Appendix B Memory-Mapped Control Registers ............747 Register Address Map ......................747 Register Bits ........................753 Appendix C Product Lineup ..................... 765 Appendix D Package Dimensions ................... 766...
Page 20: Overview And Pin Functions
Section 1 Overview and Pin Functions SH7709S Features This LSI is a single-chip RISC microprocessor that integrates a Hitachi-original RISC-type SuperH * architecture CPU as its core that has an on-chip multiplier, cache memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration such as a timer, a realtime clock, an interrupt controller, and a serial communication interface.
Page 21 Table 1.1 SH7709S Features Item Features • Original Hitachi SuperH architecture • Object code level compatible with SH-1, SH-2 and SH-3 (SH7708) • 32-bit internal data bus • General-register files  Sixteen 32-bit general registers (eight 32-bit shadow registers)  Eight 32-bit control registers ...
Page 22 Table 1.1 SH7709S Features (cont) Item Features • Cache memory 16-kbyte cache, mixed instruction/data • 256 entries, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer • Maximum 2 ways of the cache can be locked •...
Page 23 Table 1.1 SH7709S Features (cont) Item Features • Realtime clock Built-in clock, calendar functions, and alarm functions (RTC) • On-chip 32-kHz crystal oscillator circuit with a maximum resolution (interrupt cycle) of 1/256 second • Serial communi- Asynchronous mode or clock synchronous mode can be selected cation interface 0 •...
Page 24 Table 1.1 SH7709S Features (cont) Product lineup Power Supply Voltage Operating Abbr. Internal Frequency Model Name Packege ± SH7709S 3.3 0.3V 0.25V 133MHz HD6417709SBP133 240-pin CSP – 0.15V (BP-240A) 0.25V 100MHz HD6417709SF100 208-pin plastic – 0.15V LQFP (FP-208C) HD6417709SBP100 240-pin CSP (BP-240A) * 2.0 (+0.15, –0.1)V when an IRL or IRLS interrupt is used.
Page 25: Block Diagram
CMT: Compare match timer TLB: Address translation buffer CPG/WDT: Clock pulse generator/watchdog timer TMU: Timer unit CPU: Central processing unit UBC: User break controller DAC: D/A converter DMAC: Direct memory access controller H-UDI: Hitachi user-debugging interface Figure 1.1 Block Diagram...
Page 26: Pin Description
SCK1/SCPT[3] AUDSYNC/PTE[7] TxD2/SCPT[4] RD/WR SCK2/SCPT[5] WE3/DQMUU/ICIOWR/PTK[7] RTS2/SCPT[6] WE2/DQMUL/ICIORD/PTK[6] RxD0/SCPT[0] WE1/DOMLU/WE RxD1/SCPT[2] WE0/DQMLL RXD2/SCPT[4] BS/PTK[4] CTS2/IRQ5/SCPT[7] MCS[7]/PTC[7]/PINT[7] MCS[6]/PTC[6]/PINT[6] MCS[5]/PTC[5]/PINT[5] MCS[4]/PTC[4]/PINT[4] SH7709S WAKEUP/PTD[3] FP-208C RESETOUT/PTD[2] FP-208E MCS[3]/PTC[3]/PINT[3] MCS[2]/PTC[2]/PINT[2] (Top view) MCS[1]/PTC[1]/PINT[1] MCS[0]/PTC[0]/PINT[0] DRAK0/PTD[1] DRAK1/PTD[0] DREQ0/PTD[4] DREQ1/PTD[6] RESETP AN[0]/PTL[0] AN[1]/PTL[1] AN[2]/PTL[2] AN[3]/PTL[3] AN[4]/PTL[4]...
Page 27 A B C D E F G H L M N P R T U V W SH7709S BP-240A (Top view) A B C D E F G H L M N P R T U V W Note: The pin area enclosed in broken lines is an inner view.
Page 28: Pin Function
1.3.2 Pin Function Table 1.3 SH7709S Pin Function Number of Pins FP-208C BP-240A Pin Name Description FP-208E Clock mode setting Clock mode setting Vcc-RTC — RTC power supply (* XTAL2 On-chip RTC crystal oscillator pin EXTAL2 On-chip RTC crystal oscillator pin Vss-RTC —...
Page 29 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E D20/PTA[4] Data bus / input/output port A — Power supply (0 V) — — Power supply (0 V) D19/PTA[3] Data bus / input/output port A —...
Page 30 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E Address bus Address bus Address bus VssQ — Input/output power supply (0 V) Address bus VccQ — Input/output power supply (3.3 V) Address bus Address bus...
Page 31 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E Address bus VssQ — Input/output power supply (0 V) Address bus VccQ — Input/output power supply (3.3 V) Address bus BS/PTK[4] O / I/O Bus cycle start signal / input/output...
Page 32 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E CE2A/PTE[4] O / I/O Area 5 PCMCIA card enable / input/output port E CE2B/PTE[5] O / I/O Area 6 PCMCIA card enable / input/output port E...
Page 33 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E WAIT Hardware wait request RESETM Manual reset request ADTRG/PTH[5] Analog trigger / input port H IOIS16/PTG[7] Area 6 16-bit input/output / input port G ASEMD0/PTG[6]...
Page 34 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E Clock mode setting Vcc-PLL1 — PLL1 power supply (* CAP1 — PLL1 external capacitance pin Vss-PLL1 — PLL1 power supply (0 V) Vss-PLL2 — PLL2 power supply (0 V) CAP2 —...
Page 35 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E TxD2/SCPT[4] Transmit data 2 / SCI output port SCK2/SCPT[5] Serial clock 2 / SCI input/output port RTS2/SCPT[6] O / I/O Transmit request 2 / SCI...
Page 36 Table 1.3 SH7709S Pin Function (cont) Number of Pins FP-208C BP-240A Pin Name Description FP-208E MCS[0]/PTC[0]/PINT[0] O / I/O / I Mask ROM chip select / input/output port C / port interrupt DRAK0/PTD[1] O / I/O DMA request acknowledge /...
Page 37 *5 When this LSI is used on the user system alone, without an emulator and the H-UDI, hold this pin at high level. *6 B2, B1, C1, U1, V1, W1, V2, W2, W3, W17, W18, W19, V18, V19, B19, A19, B18, A18, A17, A3, A2, and A1 are NC pins.
Page 38: Cpu
2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7709S normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers—general registers, system registers, and control registers—and the registers that can be accessed differ in the two processor modes.
Page 39 R0 _ BANK0* R1 _ BANK0* R2 _ BANK0* R3 _ BANK0* R4 _ BANK0* R5 _ BANK0* R6 _ BANK0* R7 _ BANK0* MACH MACL User mode register configuration Notes: *1 R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode.
Page 40 R0_BANK1* R0_BANK0* R1_BANK1* R1_BANK0* R2_BANK1* R2_BANK0* R3_BANK1* R3_BANK0* R4_BANK1* R4_BANK0* R5_BANK1* R5_BANK0* R6_BANK1* R6_BANK0* R7_BANK1* R7_BANK0* Notes: *1 R0 functions as an index register in the indexed register-indirect addressing MACH MACH mode and indexed GBR- MACL MACL indirect addressing mode. Banked register When the RB bit of the SR register is 1, the register can...
Page 41: General Registers
Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0 to R15 Undefined Control registers MD bit = 1, RB bit = 1, BL bit = 1, I3– I0 = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC...
Page 42: System Registers
2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are four system registers, as follows.
Page 43 Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling.
Page 44: Data Formats
Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Longword Figure 2.6 Longword 2.2.2...
Page 45: Instruction Features
2.3.1 Execution Environment Data Length: The SH7709S instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
Page 46 T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below.
Page 47: Addressing Modes
2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn. (Operand is —...
Page 48 Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register @(disp:4, Effective address is register Rn contents with Byte: Rn + disp indirect with 4-bit displacement disp added. After disp is Word: Rn + disp ×...
Page 49 Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Word: PC + disp × 2 PC-relative @(disp:8, Effective address is register PC contents with with 8-bit displacement disp added. After disp is Longword: displacement zero-extended, it is multiplied by 2 (word), or...
Page 50 Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula PC-relative Effective address is sum of register PC and PC + Rn Rn contents. PC + R0 Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, —...
Page 51: Instruction Formats
2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd:...
Page 52 Table 2.3 Instruction Formats (cont) Source Destination Instruction Instruction Format Operand Operand Example nm format mmmm: register nnnn: register Rm,Rn direct direct xxxx nnnn mmmm xxxx mmmm: register nnnn: register MOV.L indirect indirect Rm,@Rn mmmm: register MACH,MACL MAC.W indirect with post- @Rm+,@Rn+ increment (multiply-and-...
Page 53 Table 2.3 Instruction Formats (cont) Source Destination Instruction Instruction Format Operand Operand Example mmmm: register nnnndddd: MOV.L format direct register Rm,@(disp,Rn) xxxx dddd nnnn mmmm indirect with displacement mmmmdddd: nnnn: register MOV.L register indirect direct @(disp,Rm),Rn with displacement d format dddddddd: GBR R0 (register MOV.L...
Page 54: Instruction Set
Instruction Set 2.4.1 Instruction Set Classified by Function The SH7709S instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation No. of Classification Types Code Function Instructions Data transfer Data transfer MOVA...
Page 55 Table 2.4 Classification of Instructions (cont) Operation No. of Classification Types Code Function Instructions Double-precision multiplication (32 × 32 Arithmetic operations bits) Signed multiplication (16 × 16 bits) (cont) MULS Unsigned multiplication (16 × 16 bits) MULU Negation NEGC Negation with borrow Binary subtraction SUBC Binary subtraction with borrow...
Page 56 Table 2.4 Classification of Instructions (cont) Operation No. of Classification Types Code Function Instructions Branch Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch...
Page 57 Table 2.5 lists the SH7709S instruction code formats. Table 2.5 Instruction Code Format Item Format Explanation Instruction OP.Sz SRC,DEST OP: Operation code mnemonic Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement MSB ↔...
Page 58 Table 2.6 lists the SH7709S data transfer instructions Table 2.6 Data Transfer Instructions Privileged Instruction Operation Code Mode Cycles T Bit imm → Sign extension — — #imm,Rn 1110nnnniiiiiiii → Rn (disp × 2 + PC) → Sign — —...
Page 59 Table 2.6 Data Transfer Instructions (cont) Privileged Instruction Operation Code Mode Cycles T Bit Rm → (R0 + Rn) — — MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) — — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 (R0 + Rm) → Sign — —...
Page 60 Table 2.7 lists the SH7709S arithmetic instructions. Table 2.7 Arithmetic Instructions Privileged Instruction Operation Code Mode Cycles T Bit Rn + Rm → Rn — — Rm,Rn 0011nnnnmmmm1100 Rn + imm → Rn — — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, —...
Page 61 Table 2.7 Arithmetic Instructions (cont) Privileged Instruction Operation Code Mode Cycles T Bit Signed operation of — 2(to 5)* — DMULS.L Rm,Rn 0011nnnnmmmm1101 Rn × Rm → MACH, MACL 32 × 32 → 64 bits Unsigned operation of — 2(to 5)* — DMULU.L Rm,Rn 0011nnnnmmmm0101 Rn ×...
Page 62 Table 2.7 Arithmetic Instructions (cont) Privileged Instruction Operation Code Mode Cycles T Bit 0–Rm → Rn — — Rm,Rn 0110nnnnmmmm1011 0–Rm–T → Rn, — Borrow NEGC Rm,Rn 0110nnnnmmmm1010 Borrow → T Rn–Rm → Rn — — Rm,Rn 0011nnnnmmmm1000 Rn–Rm–T → Rn, —...
Page 63 Table 2.8 lists the SH7709S logic operation instructions. Table 2.8 Logic Operation Instructions Privileged Instruction Operation Code Mode Cycles T Bit Rn & Rm → Rn — — Rm,Rn 0010nnnnmmmm1001 R0 & imm → R0 — — #imm,R0 11001001iiiiiiii (R0 + GBR) & imm →...
Page 64 Table 2.9 lists the SH7709S shift instructions. Table 2.9 Shift Instructions Privileged Instruction Operation Code Mode Cycles T Bit T ← Rn ← MSB — ROTL 0100nnnn00000100 LSB → Rn → T — ROTR 0100nnnn00000101 T ← Rn ← T —...
Page 65 Table 2.10 lists the SH7709S branch instructions. Table 2.10 Branch Instructions Privileged Instruction Operation Code Mode Cycles T Bit If T = 0, disp × 2 + PC → PC; — 3/1* — label 10001011dddddddd if T = 1, nop Delayed branch, if T = 0, —...
Page 66 Table 2.11 lists the SH7709S system control instructions. Table 2.11 System Control Instructions Privileged Instruction Operation Code Mode Cycles T Bit 0 → MACH, MACL — — CLRMAC 0000000000101000 0 → S — — CLRS 0000000001001000 0 → T —...
Page 67 Table 2.11 System Control Instructions (cont) Privileged Instruction Operation Code Mode Cycles T Bit (Rm) → R4_BANK, — LDC.L @Rm+, 0100mmmm11000111 Rm + 4 → Rm R4_BANK (Rm) → R5_BANK, — LDC.L @Rm+, 0100mmmm11010111 Rm + 4 → Rm R5_BANK (Rm) →...
Page 68 Table 2.11 System Control Instructions (cont) Privileged Instruction Operation Code Mode Cycles T Bit R4_BANK→ Rn — R4_BANK,Rn 0000nnnn11000010 R5_BANK→ Rn — R5_BANK,Rn 0000nnnn11010010 R6_BANK→ Rn — R6_BANK,Rn 0000nnnn11100010 R7_BANK→ Rn — R7_BANK,Rn 0000nnnn11110010 Rn–4 → Rn, SR → (Rn) —...
Page 69 Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: • When there is contention between an instruction fetch and data access • When the destination register in a load (memory-to-register) instruction is also used by the next instruction 2.
Page 70: Instruction Code Map
2.4.2 Instruction Code Map Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 0000 Rn 0000 0000 Rn 0001 0000 Rn 00MD 0010 STC SR,Rn...
Page 71 Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 0100 Rn 0000 SHLL SHAL 0100 Rn 0001 SHLR CMP/PZ Rn SHAR 0100 Rn 0010 STS.L MACH,@-Rn STS.L...
Page 72 Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 1000 00MD Rn disp MOV.B MOV.W R0,@(disp:4,Rn) R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B MOV.W @(disp:4,Rm),R0 @(disp:4,Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0...
Page 73: Processor States And Processor Modes
2.5.1 Processor States The SH7709S has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low.
Page 74: Processor Modes
From any state when From any state but hardware standby RESETP = 0 mode when RESETM = 0 RESETP = 0 Power-on reset Manual reset state state Reset state RESETP = 1 RESETM = 1 Exception-handling state Interrupt End of exception Exception transition interrupt...
Page 76: Memory Management Unit (Mmu)
Overview 3.1.1 Features The SH7709S has an on-chip memory management unit (MMU) that implements address translation. The SH7709S features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables located in external memory. It enables high- speed translation of virtual addresses into physical addresses.
Page 77 With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 Kbytes) called a page. In the following text, the SH7709S address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space.
Page 78 Virtual memory Process 1 Process 1 Physical Physical Physical memory memory memory Process 1 Virtual Process 1 Process 1 memory Physical Physical memory memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 MMU Functions...
Page 79: Sh7709S Mmu
3.1.3 SH7709S MMU Virtual Address Space (1) P0, P3, and U0 Areas For the P0, P3, and U0 areas, access through the cache and address translation using the TLB are possible. These areas can be mapped to any external memory area in units of 1- or 4-Kbyte pages.
Page 80 External memory space Area 0 Area 1 Area 2 Area 3 Area 4 Area P0 Area U0 Area 5 Area 6 Area 7 Area P1 Area P2 Address error Area P3 Area P4 Privileged mode User mode Figure 3.2 Virtual Address Space (MMUCR.AT=1)
Page 81 Physical Address Space: (1) P0, P3, and U0 Areas The P0, P3, and U0 areas can be accessed through the cache. When CCR.CE is 1, these areas will be accessed through the cache. The caching mode, copy-back or write-through, is selected by the setting of CCR.WT.
Page 82 External memory space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area P0 Area U0 Cacheable Area 5 Area 6 Area 7 H'8000 0000 H'8000 0000 Area P1 H'A000 0000 Area P2 Address error H'C000 0000 Area P3 H'E000 0000...
Page 83 When the MMU is disabled, the virtual address is used directly as the physical address. As the SH7709S supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space (see section 10, Bus State Controller (BSC)).
Page 84: Register Configuration
3.1.4 Register Configuration A register that has an undefined initial value must be initialized by software. Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration Name Abbreviation Size Initial Address Value* Page table entry register PTEH Longword Undefined...
Page 85 4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the virtual address corresponding to a TLB or address error exception. This value remains valid until the next exception or interrupt. 5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.4.
Page 86: Tlb Functions
TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.5 shows the overall TLB configuration.
Page 87 Offset Virtual address (1-kbyte page) Offset Virtual address (4-kbyte page) (15) (19) (1) (1) VPN (31–17) VPN (11–10) ASID SH SZ V TLB entry Legend: VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page.
Page 88: Tlb Indexing
3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR.
Page 89: Tlb Address Comparison
Virtual address Index Way 0–3 VPN(31–17) VPN(11–10) ASID(7–0) PPN(31–10) PR(1–0) SZ C D SH Address array Data array Figure 3.8 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB.
Page 90 The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed.
Page 91: Page Management Information
3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception.
Page 92: Mmu Functions
MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2.
Page 93: Mmu Instruction (Ldtlb)
3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16–12 specified in PTEH as the index number.
Page 94 MMUCR SV 0 0 RC 0 TF IX AT Way selection Index PTEH register PTEL register 10 8 0 V 0 PR SZ C D SH 0 ASID Write Write Way 0 to 3 VPN(31–17) VPN(11–10) ASID(7–0) PPN(31–10) PR(1–0) SZ C D SH Address array Data array...
Page 95: Avoiding Synonym Problems
1-kbyte page is explained below with reference to figure 3.11. To achieve high-speed operation of the SH7709S cache, an index number is created using virtual address bits 11–4. When a 4-kbyte page is used, virtual address bits 11–4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11–4.
Page 96 When using a 4-kbyte page Virtual address 12 11 10 Offset Virtual address (11–4) Physical address 12 11 10 Cache address Offset array Physical address (31–10) When using a 1-kbyte page Virtual address Offset Virtual address (11–4) Physical address Cache address Offset array Physical address (31–10)
Page 97: Mmu Exceptions
5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests.
Page 98: Tlb Protection Violation Exception
5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests.
Page 99: Tlb Invalid Exception
6. The contents of SR at the time of the exception are written into SSR. 7. The mode (MD) bit in SR is set to 1 to place the SH7709S in the privileged mode. 8. The block (BL) bit in SR is set to 1 to mask any further exception requests.
Page 100: Initial Page Write Exception
5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1 to place the SH7709S in the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests.
Page 101 Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs match? VPNs and ASIDs match? V = 1? TLB miss TLB invalid exception exception User mode Privileged mode User or privileged? PR check PR check 00/01 01/11 00/10 R/W? R/W?
Page 102: Processing Flow In Event Of Mmu Exception (Same Processing Flow For Address Error)
3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.13 shows the MMU exception signals in the instruction fetch mode. Handler transition processing MMU exception handler : Exception source stage = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back...
Page 103: Configuration Of Memory-Mapped Tlb
Figure 3.14 shows the MMU exception signals in the data access mode. MA WB MA WB MA WB MA WB Handler transition EX MA processing MA WB MMU exception handler MA WB : Exception source stage : Stage cancellation for instruction that has begun execution = Instruction fetch = Instruction decode...
Page 104: Data Array
The following 2 types of operations on the address array are possible. (1) Address Array Read Reads VPN, V bit, and ASID from the entry that corresponds to the entry address and way that were specified in the address field. (2) Address Array Write Writes the data set in the data field to the entry that corresponds to the entry address and way that were specified in the address field.
Page 105 (1) TLB Address Array Access Read access Address field 11110010 Data field ASID Write access Address field 11110010 Data field ASID VPN: Virtual page number ASID: Address space identifier Valid bit Don’t care bit Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data Array Access Read/write access Address field...
Page 106: Usage Examples
3.6.2 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is compared to the VPN and ASID within the TLB entry selected by the entry address and data is written to the matching way.
Page 108: Exception Handling
Section 4 Exception Handling Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction.
Page 109: Exception Vector Addresses
2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The register bank (RB) bit in SR is set to 1.
Page 110 Table 4.2 Exception Event Vectors Exception Current Exception Vector Vector Type Instruction Exception Event Priority* Order Address Offset Reset Aborted Power-on — H'A00000000 — Manual reset — H'A00000000 — H-UDI reset — H'A00000000 — General Aborted CPU address error — H'00000100 exception and retried...
Page 111: Acceptance Of Exceptions
Table 4.2 Exception Event Vectors (cont) Exception Current Exception Vector Vector Type Instruction Exception Event Priority* Order Address Offset General Completed User breakpoint trap 2 — H'00000100 exception events DMA address error — H'00000100 General Completed Nonmaskable — — H'00000600 interrupt interrupt requests...
Page 112 Pipeline Sequence: Instruction n TLB miss (data access) Instruction n + 1 TLB miss (instruction access) Instruction n + 2 RIE (reserved instruction exception) Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection Handling Order: Program Order: TLB miss (instruction n)
Page 113: Exception Codes
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next instruction when a delayed conditional branch instruction is true. 4.2.4 Exception Codes Table 4.3 lists the exception codes written to bits 11–0 of the EXPEVT register (for reset or general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify each specific exception event.
Page 114: Exception Request Masks
Table 4.3 Exception Codes (cont) Exception Type Exception Event Exception Code General interrupt requests External hardware interrupts (cont): (cont) IRL3–IRL0 = 0010 H'240 IRL3–IRL0 = 0011 H'260 IRL3–IRL0 = 0100 H'280 IRL3–IRL0 = 0101 H'2A0 IRL3–IRL0 = 0110 H'2C0 IRL3–IRL0 = 0111 H'2E0 IRL3–IRL0 = 1000 H'300...
Page 115: Register Descriptions
Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit exception code.
Page 116: Exception Handling Operation
4.4.1 Reset The reset sequence is used to power up or restart the SH7709S from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately.
Page 117: General Exceptions
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt when the BLMSK bit is 1). 3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode. 4. The RB bit in SR is set to 1.
Page 118: General Exceptions
• H-UDI Reset  Conditions: H-UDI reset command input (see section 22.4.3, H-UDI Reset)  Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to 1111.
Page 119 • TLB invalid exception  Conditions: Comparison of TLB addresses shows address match but V = 0.  Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH indicates the ASID at the time the exception occurred.
Page 120 • CPU address error  Conditions: a. Instruction fetch from odd address (4n + 1, 4n + 3) b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) d.
Page 121: Interrupts
• User break point trap  Conditions: When a break condition set in the user break controller is satisfied  Operations: When a post-execution break occurs, PC of the instruction immediately after the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of the instruction that set the break point is set in SPC.
Page 122 3. IRQ Pin Interrupts Conditions: The IRQ pin is asserted, SR.IMASK is lower than the IRQ priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC value after the instruction at which the interrupt is accepted is saved to SPC.
Page 123: Cautions
Cautions • Return from exception handling  Check the BL bit in SR with software. When SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them.  Issue an RTE instruction, which sets SPC in PC and SSR in SR, and causes a branch to the SPC address, and return from exception handling.
Page 124 • When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This will be identified as the occurrence of multiple exceptions, and may initiate reset processing.
Page 126: Cache
Section 5 Cache Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instruction/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number of entries 256 entries/way Write system...
Page 127 31–10) used for comparison during cache searches. In the SH7709S, the top three of 32 physical address bits are used as shadow bits (see section 10, Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0.
Page 128: Register Configuration
The LRU bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. Table 5.2 LRU and Way Replacement (When the cache lock function is not used) LRU (5–0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111...
Page 129: Cache Control Register 2 (Ccr2)
… … … … … … … … —: Reserved bits. Always 0 when reading. Data written here is also always 0. Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0).
Page 130 LOAD LOCK LOAD LOCK W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be loaded into Way2. In all other conditions the prefetched data will be loaded into the way pointed by LRU.
Page 131 Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Up in a Cache Miss DSP bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be replaced Depends on LRU (Table 5.2) Depends on LRU (Table 5.2) Depends on LRU (Table 5.6) Depends on LRU (Table 5.7) Depends on LRU (Table 5.8) * : don't care...
Page 132: Cache Operation
Cache Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.4 illustrates the method by which the cache is searched.
Page 133 Virtual address 12 11 4 3 2 1 0 Entry selection Longword (LW) selection Ways 0–3 Ways 0–3 V U Tag address Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.4 Cache Search Scheme (Normal Mode)
Page 134: Read Access
5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is the one least recently used.
Page 135: Coherency Of Cache And External Memory
PA (31–4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31–4): Physical address written to external memory Longword 0–3: The line of cache data to be written to external memory Figure 5.5 Write-Back Buffer Configuration 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory.
Page 136: Data Array
Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address and way that were specified in the address field. No associative operation will be performed, regardless of the value of the associative bit (the A bit). (2) Address Array Write (Without associative operation) Writes the tag address, LRU, U bit, and V bit specified in the data field to the entry that corresponds to the entry address and way that were specified in the address field.
Page 137 (2) Data Array Write Writes the longword data set in the data field into the entry that corresponds to the entry address and way that were specified in the address field. The longword data will be written to the entry at the position selected by the L bits (3-2) of the address field.
Page 138: Examples Of Usage
5.4.3 Examples of Usage (1) Invalidating a Specific Entry A specific cache entry can be invalidated by writing a 0 to the entry's U and V bits. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address.
Page 140: Interrupt Controller (Intc)
• External devices can be notified that an interrupt has been received (IRQOUT): When the SH7709S has released the bus, the external bus master can be notified that an external interrupt, an on-chip peripheral module interrupt, or a memory refresh request has occurred,...
Page 141: Block Diagram
: Refresh requests in the bus state controller : Interrupt control register IPRA–IPRE : Interrupt priority registers A–E : Status register DMAC : Direct memory access controller : Analog-to-digital converter H-UDI : Hitachi user-debugging interface Figure 6.1 Block Diagram of INTC...
Page 142: Pin Configuration
6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 INTC Pins Name Abbreviation Description Nonmaskable interrupt input pin Input of interrupt request signal, not maskable by the interrupt mask bits in Interrupt input pins IRQ5–IRQ0 Input of interrupt request signals, IRL3–IRL0 maskable by the interrupt mask bits in IRLS3-IRLS0...
Page 143: Register Configuration
6.1.4 Register Configuration The INTC has the 12 registers listed in table 6.2. Table 6.2 INTC Registers Access Name Abbr. Initial Value Address Size Interrupt control register 0 ICR0 H'FFFFFEE0 Interrupt control register 1 ICR1 H'0000 H'04000010 (H'A4000010)* Interrupt control register 2 ICR2 H'0000 H'04000012...
Page 144: Interrupt Sources
Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL,PINT, and on-chip peripheral modules. Each interrupt has a priority level (0–16), with 0 the lowest and 16 the highest. Priority level 0 masks an interrupt. 6.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16.
Page 145: Irl Interrupts
IRL0/IRLS3–IRLS0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 6.2 shows an example of IRL interrupt connection. Table 6.3 shows IRL/IRLS pins and interrupt levels. SH7709S Priority Interrupt IRL3 to IRL0...
Page 146 IRL3–IRL0/IRLS3–IRLS0 Pins and Interrupt Levels Table 6.3 IRL3/ IRL2/ IRL1/ IRL0/ IRLS3 IRLS2 IRLS1 IRLS0 Interrupt Priority Level Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request...
Page 147: Pint Interrupts
• Direct memory access controller (DMAC) • Analog-to-digital converter (ADC) • Hitachi user-debugging interface (H-UDI) Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value of the INTEVT or INTEVT2 register as a branch offset.
Page 148: Interrupt Exception Handling And Priority
6.2.6 Interrupt Exception Handling and Priority Tables 6.4 and 6.5 list the codes for the interrupt event registers (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned a unique code. The start address of the interrupt service routine is common to each interrupt source.
Page 149 Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority H'1C0 (H'1C0) — — High H-UDI H'5E0 (H'5E0) — — IRQ0 H'200–3C0* (H'600) 0–15 (0)
Page 150 Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) (cont) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority H'480 (H'480) 0–15 (0) IPRA (3–0) High High H'4A0 (H'4A0) H'4C0 (H'4C0) SCI0 H'4E0 (H'4E0)
Page 151 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority H'1C0 (H'1C0) — — High H-UDI H'5E0 (H'5E0) — — IRL(3:0) = 0000 H'200 (H'200) —...
Page 152 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) (cont) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority SCIF ERI2 H'200–3C0* (H'900) 0–15 (0) IPRE (7–4) High High RXI2 H'200–3C0*...
Page 153 Table 6.6 Interrupt Levels and INTEVT Codes Interrupt level INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0...
Page 154: Intc Registers
INTC Registers 6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE) Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in standby mode.
Page 155: Interrupt Control Register 0 (Icr0)
6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. This register is initialized to H'0000 or H'8000 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 156: Interrupt Control Register 1 (Icr1)
6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 157 Bit 12—IRLS Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the IRQLVL bit is 1. Bit 12: IRLSEN Description Pins IRLS3–IRLS0 disabled (Initial value) Pins IRLS3–IRLS0 enabled Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
Page 158 Bits 5 and 4—IRQ2 Sense Select (IRQ21S, IRQ20S): Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at the low level. Bit 5: IRQ21S Bit 4: IRQ20S Description An interrupt request is detected at IRQ2 input falling edge (Initial value) An interrupt request is detected at IRQ2 input rising edge An interrupt request is detected at IRQ2 input low level...
Page 159: Interrupt Control Register 2 (Icr2)
6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit readable/writable register that sets the detection mode for external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: PINT15S PINT14S PINT13S PINT14S PINT11S PINT10S PINT9S PINT8S Initial value:...
Page 160: Pint Interrupt Enable Register (Pinter)
6.3.5 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit readable/writable register that enables interrupt requests input to external interrupt input pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: PINT15E PINT14E PINT13E PINT12E PINT11E PINT10E PINT9E PINT8E Initial value:...
Page 161: Interrupt Request Register 0 (Irr0)
6.3.6 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode.
Page 162 Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. Bit 4: IRQ4R Description No interrupt request input to IRQ4 pin (Initial value) Interrupt request input to IRQ4 pin Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether there is interrupt request input to...
Page 163: Interrupt Request Register 1 (Irr1)
6.3.7 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests have been generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit: TXI1R BRI1R...
Page 164: Interrupt Request Register 2 (Irr2)
Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request has been generated. Description it 3: DEI3R DEI3 interrupt request not generated (Initial value) DEI3 interrupt request generated Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request has been generated.
Page 165 Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has been generated. Description it 4: ADIR ADI interrupt request not generated (Initial value) ADI interrupt request generated Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request has...
Page 166: Intc Operation
Notes: 1. The interrupt mask bits (I3–I0) in the status register (SR) are not changed by acceptance of an interrupt in the SH7709S. 2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the high level.
Page 167 Program execution state ICR1.MAI = 1? NMI = low? Interrupt generated? ICR1.BLMSK = 1? SR.BL= 0 or sleep mode? NMI? NMI? Level 15 interrupt? Level 14 interrupt? IRQOUT = low I3–I0 level Level 1 14 or lower? interrupt? Set interrupt cause in I3–I0 level INTEVT, INTEVT2 13 or lower?
Page 168: Multiple Interrupts
6.4.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler.
Page 169 Table 6.8 Interrupt Response Time Number of States Peripheral Item PINT Modules Notes 0.5 × Icyc 0.5 × Icyc 0.5 × Icyc 0.5 × Icyc Time for priority + 0.5 × Bcyc + 1 × Bcyc + 1.5 × Pcyc* decision and SR mask bit comparison + 0.5 ×...
Page 170 Table 6.8 Interrupt Response Time (cont) Number of States Peripheral Item PINT Modules Notes Response Total (5.5 + X) (5.5 + X) (5.5 + X) (5.5 + X) × Icyc × Icyc × Icyc × Icyc time + 0.5 × Bcyc + 1 ×...
Page 171 Interrupt Start of interrupt acceptance handling 0.5 × Icyc + 0.5 × Bcyc + 2 × Pcyc 5 × Icyc Instruction (instruction replaced by interrupt exception handling) Overrun fetch First instruction of interrupt handler Instruction fetch: Instruction is fetched from memory in which program is stored. Instruction decode: Fetched instruction is decoded.
Page 172: User Break Controller
Section 7 User Break Controller Overview The user break controller (UBC) provides functions that simplify program debugging. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop timing during instruction fetches.
Page 173: Block Diagram
7.1.2 Block Diagram Figure 7.1 shows a block diagram of the UBC. Access Control Access comparator BBRA BARA Address comparator BAMRA ASID comparator BASRA Channel A Access BBRB comparator BARB Address comparator BAMRB ASID comparator BASRB BDRB Data comparator BDMRB Channel B BETR BRSR...
Page 174: Register Configuration
7.1.3 Register Configuration Table 7.1 Register Configuration Access Name Abbr. Initial Value* Address Size Location Break address register A BARA H'00000000 H'FFFFFFB0 Break address mask BAMRA R/W H'00000000 H'FFFFFFB4 register A Break bus cycle register A BBRA H'0000 H'FFFFFFB8 Break address register B BARB H'00000000 H'FFFFFFA0...
Page 175: Register Descriptions
Register Descriptions 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. A power-on reset initializes BARA to H'00000000. Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value:...
Page 176: Break Address Mask Register A (Bamra)
7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. A power-on reset initializes BAMRA to H'00000000. Bit: BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 Initial value: R/W: Bit:...
Page 177: Break Bus Cycle Register A (Bbra)
7.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A.
Page 178 Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the bus cycle of the channel A break condition. Bit 3: RWA1 Bit 2: RWA0 Description Condition comparison is not performed (Initial value) The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle...
Page 179: Break Address Register B (Barb)
7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. A power-on reset initializes BARB to H'00000000. Bit: BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 Initial value: R/W: Bit:...
Page 180: Break Address Mask Register B (Bamrb)
7.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. A power-on reset initializes BAMRB to H'00000000. Bit: BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 Initial value: R/W: Bit:...
Page 181: Break Data Register B (Bdrb)
7.2.6 Break Data Register B (BDRB) BDRB is a 32-bit read/write register. A power-on reset initializes BDRB to H'00000000. Bit: BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value: R/W: Bit: BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: R/W: Bit:...
Page 182: Break Data Mask Register B (Bdmrb)
7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. A power-on reset initializes BDMRB to H'00000000. Bit: BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit:...
Page 183: Break Bus Cycle Register B (Bbrb)
7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel B.
Page 184 Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select the read cycle or write cycle as the bus cycle of the channel B break condition. Bit 3: RWB1 Bit 2: RWB0 Description Condition comparison is not performed (Initial value) The break condition is the read cycle The break condition is the write cycle The break condition is the read cycle or write cycle Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for...
Page 185: Break Control Register (Brcr)
7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4.
Page 186 Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not. Bit 21: BASMA Description All BASRA bits are included in break condition, ASID is checked (Initial value) No BASRA bits are included in break condition, ASID is not checked Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7-...
Page 187 Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. Bit 13: SCMFDA Description...
Page 188 Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. Bit 6: PCBB Description PC break of channel B is set before instruction execution (Initial value) PC break of channel B is set after instruction execution Bits 5 and 4—Reserved: These bits are always read as 0.
Page 189: Execution Times Break Register (Betr)
7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 – 1 times. A power-on reset initializes BETR to H'0000. When a break condition is satisfied, it decreases the BETR. A break is issued when the break condition is satisfied after the BETR becomes H'0001.
Page 190: Branch Source Register (Brsr)
7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets.
Page 191: Branch Destination Register (Brdr)
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Bits 30 to 28: Description Even PID indicates the instruction buffer number. PiD+2 indicates the instruction buffer number Bits 27 to 0—Branch Source Address (BSA27–BSA0): These bits store the last fetched address before branch.
Page 192: Break Asid Register A (Basra)
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading BRDR. Bit 31: DVF Description The value of BRDR register is invalid The value of BRDR register is valid Bits 30 to 28—Reserved: These bits are always read as 0.
Page 193: Operation Description
Operation Description 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the break address registers (BARA and BARB) and break ASID registers (BASRA and BASRB). The masked addresses are set in the break address mask registers (BAMRA and BAMRB).
Page 194: Break On Instruction Fetch Cycle
7.3.2 Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel.
Page 195: Sequential Break
3. When the data value is included in the break conditions on B channel: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match.
Page 196: Pc Trace
4. When data access (address + data) is specified as a break condition: The PC value is the start address of the instruction that follows the instruction already executed when break processing started up. When a data value is added to the break conditions, the place where the break will occur cannot be specified exactly.
Page 197: Usage Examples
4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR, longword access should be used.
Page 198 2. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode •...
Page 199 4. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode •...
Page 200 6. Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode •...
Page 201: Notes
Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications: BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode •...
Page 202 5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR are read. 6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as follows: a. Break and instruction fetch exceptions: Instruction fetch exception occurs first. b.
Page 204: Power-Down Modes
In the power-down modes, all CPU and some on-chip peripheral module functions are halted. This lowers power consumption. 8.1.1 Power-Down Modes The SH7709S has the following power-down modes and function: 1. Sleep mode 2. Standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, SCIF, and IrDA on- chip peripheral modules) 4.
Page 205 Table 8.1 Power-Down Modes State On-Chip Transition Reg- On-Chip Peripheral External Canceling Mode Conditions CPG CPU ister Memory Modules Pins Memory Procedure 1. Interrupt Sleep Execute SLEEP Runs Halts Held Held Held Refresh mode instruction with 2. Reset STBY bit cleared to 0 in STBCR 1.
Page 206: Pin Configuration
8.1.2 Pin Configuration Table 8.2 lists the pins used for the power-down modes. Table 8.2 Pin Configuration Pin Name Abbreviation I/O Description Processing state 1 STATUS1 Operating state of the processor. Processing state 0 STATUS0 HH: Reset, HL: Sleep mode, LH: Standby mode, LL: Normal operation WAKEUP Wakeup from...
Page 207 Bit 7—Standby (STBY): Specifies transition to standby mode. Bit 7: STBY Description Executing SLEEP instruction puts chip into sleep mode (Initial value) Executing SLEEP instruction puts chip into standby mode Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—Standby Crystal (STBXTL): Specifies halting or operating of the clock pulse generator in standby mode.
Page 208: Standby Control Register 2 (Stbcr2)
8.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a readable/writable 8-bit register that sets the power- down mode. STBCR2 is initialized to H'00 by a power-on reset. Bit:  MDCHG MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 Initial value: R/W: Bit 7—Reserved: The write value set in the program should always be 1.
Page 209 Bit 3: MSTP6 Description DAC runs (Initial value) Clock supply to DAC halted Bit 2—Module Stop 5 (MSTP5): Specifies halting of the clock supply to the ADC (an on-chip peripheral module). When the MSTP5 bit is set to 1, the supply of the clock to the ADC is halted and all registers are initialized.
Page 210: Sleep Mode
Sleep Mode 8.3.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the CKIO and CKIO2 pins.
Page 211: Standby Mode
Standby Mode 8.4.1 Transition to Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip switches from the program execution state to standby mode. In standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well.
Page 212: Canceling Standby Mode
8.4.2 Canceling Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, or on-chip peripheral module) or a reset. Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL, IRQ, PINT* , or on-chip peripheral module (except interval timer)* interrupt, the clock will be supplied to the entire chip and standby mode canceled after the time set in the...
Page 213: Clock Pause Function
Canceling with a Reset: Standby mode is canceled by a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO and CKIO2 pins. 8.4.3 Clock Pause Function In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed.
Page 214: Module Standby Function
Module Standby Function 8.5.1 Transition to Module Standby Function Setting the standby control register MSTP8–MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. The module standby function holds the state prior to halting the external pins of the on-chip peripheral modules.
Page 215: Timing Of Status Pin Changes
Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 through 8.8. 8.6.1 Timing for Resets Power-On Reset CKIO, CKIO2* PLL settling time RESETP Normal* Reset* Normal* STATUS RESETOUT 0 to 5 Bcyc* 0 to 30 Bcyc* Notes: *1 Reset: HH (STATUS1 high, STATUS0 high)
Page 216 Manual Reset CKIO, CKIO2* RESETM Normal* Reset* Normal* STATUS RESETOUT 0 Bcyc or more* 0 to 30 Bcyc* Notes: *1 In a manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. *2 Reset: HH (STATUS1 high, STATUS0 high) *3 Normal: LL (STATUS1 low, STATUS0 low)
Page 217: Timing For Canceling Standby
8.6.2 Timing for Canceling Standby Standby to Interrupt Oscillation stops Interrupt request WDT overflow CKIO, CKIO2* WDT count Normal* Standby* Normal* STATUS WAKEUP Notes: *1 Standby: LH (STATUS1 low, STATUS0 high) *2 Normal: LL (STATUS1 low, STATUS0 low) *3 The CKIO2 output is available only in clock modes 0, 1, and 2. Figure 8.4 Standby to Interrupt STATUS Output...
Page 218 Standby to Power-On Reset Oscillation stops Reset CKIO, CKIO2* RESETP* STATUS Normal* Standby* Reset* Normal* 0 to 10 Bcyc* 0 to 30 Bcyc* Notes: *1 When standby mode is cleared with a power-on reset, the WDT does not count. Keep RESETP low during the PLL’s oscillation settling time. *2 Undefined *3 Reset: HH (STATUS1 high, STATUS0 high)
Page 219: Timing For Canceling Sleep Mode
Standby to Manual Reset Oscillation stops Reset CKIO, CKIO2* RESETM* STATUS Normal* Standby* Reset* Normal* 0 to 20 Bcyc* Notes: *1 When standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL’s oscillation settling time. *2 Reset: HH (STATUS1 high, STATUS0 high) *3 Standby: LH (STATUS1 low, STATUS0 high)
Page 220 Sleep to Power-On Reset Reset CKIO, CKIO2* RESETP* STATUS Normal* Sleep* Reset* Normal* 0 to 10 Bcyc* 0 to 30 Bcyc* Notes: *1 When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL’s oscillation settling time. *2 Undefined *3 Reset: HH (STATUS1 high, STATUS0 high)
Page 221 Sleep to Manual Reset Reset CKIO, CKIO2* RESETM* Normal* STATUS Sleep* Reset* Normal* 0 to 80 Bcyc* 0 to 30 Bcyc* *1 Keep RESETM low until STATUS becomes reset. Note: *2 Reset: HH (STATUS1 high, STATUS0 high) *3 Sleep: HL (STATUS1 high, STATUS0 low) *4 Normal: LL (STATUS1 low, STATUS0 low) *5 Bcyc: Bus clock cycle...
Page 222: Hardware Standby Mode
Hardware Standby Mode 8.7.1 Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the standby mode entered on execution of a SLEEP instruction ((software) standby mode).
Page 223: Canceling Hardware Standby Mode
8.7.2 Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the CPU begins power-on reset processing.
Page 224 Rcyc: EXTAL2 (32.768 kHz) cycle CKIO, CKIO2* RESETP STATUS Normal* Standby* Reset* Undefined 2 Rcyc or more* 0–10Bcyc* Notes: *1 Reset: HH (STATUS1 high, STATUS0 high) *2 Standby: LH (STATUS1 low, STATUS0 high) *3 Normal: LL (STATUS1 low, STATUS0 low) *4 Bcyc: Bus clock cycle *5 Rcyc:...
Page 225 CKIO, CKIO2* RESETP STATUS Standby Normal* Standby* Reset* Undefined 0–10 Bcyc* WDT operation 2 Rcyc or more* Notes: *1 Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Rcyc: EXTAL2 (32.768 kHz) cycle The CKIO2 output is available only in clock modes 0, 1, and 2.
Page 226: On-Chip Oscillation Circuits
Section 9 On-Chip Oscillation Circuits Overview The on-chip oscillation circuits consist of a clock pulse generator (CPG) block and a watchdog timer (WDT) block. The WDT is a single-channel timer that counts the clock settling time and is used when clearing standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer.
Page 227: Overview Of Cpg
Overview of CPG 9.2.1 CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1. Clock pulse generator Divider 1 × 1 CAP1 × 1/2 Internal PLL circuit 1 × 1/3 clock (Iφ) (× 1, 2, 3, 4, ×...
Page 228 The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, sextuples, or leaves unchanged the input clock frequency from the CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the CKIO pin.
Page 229: Cpg Pin Configuration
9.2.2 CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 CPG Pins and Functions Pin Name Symbol Description Mode control Set the clock operating mode. pins Crystal I/O pins XTAL Connects a crystal oscillator. (clock input pins) EXTAL Connects a crystal oscillator.
Page 230: Clock Operating Modes
Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes Pin Values Clock I/O PLL2 PLL1 Divider 1 Divider 2 CKIO...
Page 231 output of the chip’s CKIO pin. Consequently, if a large number of ICs are operating on the clock cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by distributing the clocks to each one.
Page 232 Table 9.4 Available Combinations of Clock Mode and FRQCR Values (cont) Clock Clock Rate* Input Frequency CKIO Frequency Mode FRQCR PLL1 PLL2 (I:B:P) Range Range 1, 2 H'0100 ON (× 1) ON (× 4) 4:4:4 6.25 MHz to 8.34 MHz 25 MHz to 33.34 MHz H'0101 ON (×...
Page 233 Cautions: 1. The frequency of the internal clock (Iφ) becomes: • The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1. • Do not set the internal clock frequency lower than the CKIO pin frequency. 2.
Page 234: Register Descriptions
Register Descriptions 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify the frequency multiplication ratio of PLL circuit 1 and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register.
Page 235 Bits 14, 3, and 2—Internal Clock Frequency Division Ratio (IFC): These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. Bit 14: IFC2 Bit 3: IFC1 Bit 2: IFC0 Description ×...
Page 236: Changing The Frequency
Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication ratio of PLL circuit 1 or by changing the division ratios of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below.
Page 237: Overview Of Wdt
Overview of WDT 9.6.1 Block Diagram of WDT Figure 9.2 shows a block diagram of the WDT. Standby Standby Standby mode cancellation control Peripheral clock Internal Reset Divider reset control request Clock selection Clock selector Overflow Interrupt Interrupt Clock request control WTCSR WTCNT...
Page 238: Wdtregisters
WDT Registers 9.7.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the selected clock. WTCNT differs from other registers in that it is more difficult to write to. See section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode.
Page 239 Bit 7: TME Description Timer disabled: Count-up stops and WTCNT value is retained (Initial value) Timer enabled Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an interval timer. Bit 6: WT/IT Description Used as interval timer (Initial value) Used as watchdog timer...
Page 240: Notes On Register Access
Overflow Period Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio (when Pφ = 15 MHz) 17 µs (Initial value) 68 µs 273 µs 1/16 546 µs 1/32 1/64 1.09 ms 1/256 4.36 ms 1/1024 17.48 ms 1/4096 69.91 ms Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be...
Page 241: Using The Wdt
WDT. When the STBY bit remains at 1, the SH7709S again enters standby mode when the WDT has counted up to H'80. This standby mode can be canceled by a power-on reset.
Page 242: Using Watchdog Timer Mode
9.8.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2–CKS0 bits, and set the initial value of the counter in the WTCNT counter.
Page 243: Notes On Board Design
Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.1 to 1 µF as a passive capacitor for each V pair. Mount the passive capacitors close to the SH7709S power supply pins, and use components with a frequency characteristic suitable for the chip’s operating frequency, as well as a suitable capacitance value.
Page 244 Avoid crossing signal lines (PLL2) Power supply CAP2 (PLL2) Reference values C1 = 470 pF (PLL1) C2 = 470 pF CAP1 (PLL1) Figure 9.5 Points for Attention when Using PLL Oscillator Circuit...
Page 246: Section 10 Bus State Controller (Bsc)
Section 10 Bus State Controller (BSC) 10.1 Overview The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable the chip to link directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit.
Page 247  Bus sizing function for I/O bus width (only in little-endian mode) • Refresh function  Refresh cycles will be automatically maintained in sleep mode even after the external bus frequency is reduced to 1/4 of its normal operating frequency •...
Page 248: Block Diagram
10.1.2 Block Diagram Figure 10.1 shows a block diagram of the bus state controller. interface WCR1 Wait WAIT controller WCR2 CS0, CS6–CS2, Area CE2A, CE2B BCR1 controller MCS0–MCS7 BCR2 RD/WR WE3–WE0 RASxx CASx Memory controller ICIORD, ICIOWR MCSCRn IOIS16 RFCR RTCNT Refresh Interrupt...
Page 249: 10.1.3 Pin Configuration
10.1.3 Pin Configuration Table 10.1 shows the BSC pin configuration. Table 10.1 BSC Pins Pin Name Signal Description Address bus A25–A0 Address output Data bus D15–D0 Data I/O D31–D16 Data I/O when using 32-bit bus width Bus cycle start Shows start of bus cycle. During burst transfers, asserted every data cycle.
Page 250 Table 10.1 BSC Pins (cont) Pin Name Signal Description WE3/DQMUU/ Data enable 3 When memory other than synchronous DRAM and ICIOWR PCMCIA is used, D31–D24 write strobe signal. When synchronous DRAM is used, selects D31– D24. When PCMCIA is used, strobe signal indicating I/O write.
Page 251: Register Configuration
10.1.4 Register Configuration The BSC has 21 registers (table 10.2). Synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states, and refreshes devices. Table 10.2 BSC Registers Name Abbr. Initial Value* Address Bus Width Bus control register 1...
Page 252: Area Overview
3, Memory Management Unit, which describes area allocation for physical space. As shown in table 10.3, the SH7709S can be connected directly to six memory/PCMCIA interface areas, and it outputs chip select signals (CS0, CS2–CS6, CE2A, CE2B) for each of them. CS0 is asserted during area 0 access;...
Page 253 Table 10.3 Physical Address Space Map Area Connectable Memory Physical Address Capacity Access Size Ordinary memory , burst ROM H'00000000 to H'03FFFFFF 64 Mbytes 8, 16, 32 H'00000000 + H'20000000 × n to Shadow n: 1–6 H'03FFFFFF + H'20000000 × n Internal I/O registers H'04000000 to H'07FFFFFF 64 Mbytes 8, 16, 32...
Page 254 Figure 10.3 Physical Space Allocation Memory Bus Width: The memory bus width in the SH7709S can be set for each area. In area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset.
Page 255: Pcmcia Support
10.1.6 PCMCIA Support The SH7709S supports PCMCIA standard interface specifications in physical space areas 5 and 6. The interfaces supported are basically the “IC memory card interface” and “I/O card interface” stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1).
Page 256 Table 10.6 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin — Ground — Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 257 Table 10.6 PCMCIA Support Interface (cont) IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin I/O Data I/O Data I/O Data I/O Data IOIS16 IOIS16 Write protect 16-bit I/O port Ground Ground —...
Page 258: Bsc Registers
Table 10.6 PCMCIA Support Interface (cont) IC Memory Card Interface I/O Card Interface Pin Signal I/O Function Signal I/O Function SH7709S Pin Attribute memory Attribute memory — space select space select SPKR BVD2 Battery voltage Digital voice signal — detection...
Page 259 The endian for all physical spaces is decided by this bit, which is read-only. Bit 11: ENDIAN Description (On reset) Endian setting external pin (MD5) is low. Indicates the SH7709S is set as big-endian (On reset) Endian setting external pin (MD5) is high. Indicates the SH7709S...
Page 260 Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst ROM in physical space area 0. When burst ROM is used, these bits set the number of burst transfers. Bit 10: A0BST1 Bit 9: A0BST0 Description Access area 0 accessed as ordinary memory (Initial value)
Page 261 Bit 6: A6BST1 Bit 5: A6BST0 Description Access area 6 accessed as ordinary memory (initial value) Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16.
Page 262: Bus Control Register 2 (Bcr2)
Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as PCMCIA space. Bit 0: A6PCM Description Physical space area 6 accessed as ordinary memory (Initial value) Physical space area 6 accessed as PCMCIA space 10.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that selects the bus size of each area and whether an 8-bit port is used or not.
Page 263: Wait State Control Register 1 (Wcr1)
Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Port A / B Description Not used Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Longword (32-bit) size Used Reserved (Setting prohibited) Byte (8-bit) size Word (16-bit) size Reserved (Setting prohibited) 10.2.3 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the...
Page 264: Wait State Control Register 2 (Wcr2)
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling timing. Bit 15: WAITSEL Description Setting to 1 when using the WAIT signal* (Initial value) Sampled WAIT signal at fall of CKIO Note: * Operation is not guaranteed if WAIT is asserted while WEITSEL = 0. Bits 14, 3, and 2 —Reserved: These bits are always read as 0.
Page 265 Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states inserted in physical space area 6. Also specify the number of states for burst transfer. Description Burst Cycle First Cycle (Excluding First Cycle) Bit 15: Bit 14: Bit 13: Inserted...
Page 266 Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states inserted in physical space area 4. Description Inserted Wait State WAIT Pin Bit 9: A4W2 Bit 8: A4W1 Bit 7: A4W0 Ignored Enabled Enabled Enabled Enabled Enabled...
Page 267 Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted in physical space area 2. • For Ordinary Memory Description WAIT Pin Bit 4: A2W0 Bit 3: A2W0 Inserted Wait States Ignored Enabled Enabled Enabled (Initial value) •...
Page 268: Individual Memory Control Register (Mcr)
10.2.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit readable/writable register that specifies RAS and CAS timing for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 269 Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is selected as connected memory, these bits set the bank active read/write command delay time. Bit 13: RCD1 Bit 12: RCD0 Description 1 cycle (Initial value) 2 cycles 3 cycles 4 cycles Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): Set the synchronous DRAM write-precharge delay time.
Page 270 For Synchronous DRAM Interface: Bit6: Bit5: Bit 4: Bit 3: AMX3 AMX2 AMX1 AMX0 Description The row address begins with A10. (The A10 value is output at A1 when the row address is output. 4M × 16-bit × 4-bank products) The row address begins with A11.
Page 271: Pcmcia Control Register (Pcr)
Bit 1—Refresh Mode (RMODE): Selects whether to perform an ordinary refresh or a self- refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, an auto-refresh is performed on synchronous DRAM at the period set by refresh-related registers RTCNT, RTCOR, and RTCSR.
Page 272 Bit 15—Area 6 Wait Control (A6W3): Specifies the number of inserted wait states for area 6 combined with bits A6W2–A6W0 in WCR2. Also specifies the number of transfer states in burst transfer. Clear this bit to 0 when area 6 is not set to PCMCIA. First Cycle Burst Cycle Number of...
Page 273 Bits 11, 7, and 6—Area 5 Address OE/WE Assert Delay (A5TED2, A5TED1, A5TED0): Specify the delay time from address output to OE/WE assertion for the PCMCIA interface connected to area 5. Bit 11: Bit 7: Bit 6: A5TED2 A5TED1 A5TED0 Description 0.5-cycle delay (Initial value)
Page 274 Bits 9, 3, and 2—Area 5 OE/WE Negate Address Delay (A5TEH2, A5TEH1, A5TEH0): Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to area 5. Bit 9: Bit 3: Bit 2: A5TEH2 A5TEH1 A5TEH0 Description 0.5-cycle delay (Initial value) 1.5-cycle delay...
Page 275: Synchronous Dram Mode Register (Sdmr)
10.2.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is an 8-bit write-only register that is written to via the synchronous DRAM address bus. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before accessing the synchronous DRAM. Writes to the synchronous DRAM mode register use the address bus rather than the data bus.
Page 276: Refresh Timer Control/Status Register (Rtcsr)
10.2.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 277 Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified ratio. RTCOR must be set before setting CKS2-CKS0. Description Bit 5: CKS2 Bit 4: CKS1...
Page 278: Refresh Timer Counter (Rtcnt)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value in RFCR overflows the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description Count limit value is 1024...
Page 279: Refresh Time Constant Register (Rtcor)
10.2.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) specifies the upper-limit value of RTCNT. The values of RTCOR and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the individual memory control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the CMF bit is set.
Page 280: 10.2.12 Cautions On Accessing Refresh Control Related Registers
Bit: Initial value: R/W: — — — — — — Bit: Initial value: R/W: 10.2.12 Cautions on Accessing Refresh Control Related Registers RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations (figure 10.5).
Page 281: Mcs0 Control Register (Mcscr0)
10.2.13 MCS0 Control Register (MCSCR0) The MCS0 control register (MCSCR0) is a 16-bit readable/writable register that specifies the MCS[0] pin output conditions. MCSCR0 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 282: Mcs1 Control Register (Mcscr1)
10.2.14 MCS1 Control Register (MCSCR1) The MCS1 control register (MCSCR1) specifies the MCS[1] pin output conditions. The bit configuration and functions are the same as those of MCSCR0. 10.2.15 MCS2 Control Register (MCSCR2) The MCS2 control register (MCSCR2) specifies the MCS[2] pin output conditions. The bit configuration and functions are the same as those of MCSCR0.
Page 283: Bsc Operation
Endian/Access Size and Data Alignment The SH7709S supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on reset.
Page 284 Table 10.8 16-Bit External Device/Big-Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31– D23– Operation D15–D8 D7–D0 DQMUU DQMUL DQMLU DQMLL Byte access at 0 — — Data — Asserted — 7–0 Byte access at 1 —...
Page 285 Table 10.9 8-Bit External Device/Big-Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31– D23– D15– Operation D7–D0 DQMUU DQMUL DQMLU DQMLL Byte access at 0 — — — Data 7–0 Asserted Byte access at 1 —...
Page 286 Table 10.10 32-Bit External Device/Little-Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, Operation D31–D24 D23–D16 D15–D8 D7–D0 DQMUU DQMUL DQMLU DQMLL Byte — — — Data Asserted access at 0 7–0 Byte — — Data —...
Page 287 Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31– D23– D15– Operation D7–D0 DQMUU DQMUL DQMLU DQMLL Byte access at 0 — — — Data 7–0 Asserted Byte access at 1 —...
Page 288: Description Of Areas
10.3.2 Description of Areas Area 0: Area 0 physical address bits A28–A26 are 000. Address bits A31–A29 are ignored and the address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space.
Page 289 Area 3: Area 3 physical address bits A28–A26 are 011. Address bits A31–A29 are ignored and the address range is H'0C000000 + H'20000000 × n – H'0FFFFFFF + H'20000000 × n (n = 0–6 and n = 1–6 are the shadow spaces). Ordinary memories such as SRAM and ROM, as well as synchronous DRAM, can be connected to this space.
Page 290 When the area 5 space is accessed and ordinary memory is connected, the CS5 signal is asserted. The RD signal that can be used as OE and the WE0–WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE1 signal are asserted.
Page 291: Basic Interface
10.3.3 Basic Interface Basic Timing: The basic interface of the SH7709S uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 10.6 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle.
Page 292 CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 Figure 10.6 Basic Timing of Basic Interface...
Page 293 Figures 10.7, 10.8, and 10.9 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k × 8-bit SH7709S SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 10.7 Example of 32-Bit Data-Width Static RAM Connection...
Page 294 128k × 8-bit SH7709S SRAM I/O7 I/O0 I/O7 I/O0 Figure 10.8 Example of 16-Bit Data-Width Static RAM Connection...
Page 295 128k × 8-bit SH7709S SRAM I/O7 I/O0 Figure 10.9 Example of 8-Bit Data-Width Static RAM Connection...
Page 296 Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait Control Register 2 (WCR2).
Page 297 When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle.
Page 298 Wait states inserted by WAIT signal CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 WAIT Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1)
Page 299: Synchronous Dram Interface
DRAM space. Note, however, that synchronous DRAM must not be accessed when clock ratio Iφ:Bφ = 1:1. With the SH7709S, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. A data bus width of 16 or 32 bits can be selected. A 16-bit burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write.
Page 300 64M synchronous DRAM (1M × 16-bit × 4-bank) SH7709S CKI0 RAS3x CASx RD/WR DQ15 DQMUU DQMU DQMUL DQML DQMLU DQMLL DQ15 DQMU Note : "x" is U or L DQML Figure 10.12 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)
Page 301 Connection should therefore be made in the following order: with a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of the SH7709S, then connect pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to...
Page 302 Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output Setting External Address Pins Memory Output A1 to Width Type Timing A10 A11 A12 A13 A14 A15 A16 32 bits 4M × Column A1 to A10 A11 L/H* A13 A23 A24* A25* 16bits ×...
Page 303 Table 10.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output (cont) Setting External Address Pins Memory Output A1 to Width Type Timing A10 A11 A12 A13 A14 A15 A16 2M × Column A1 to A10 L/H* A22* A23* 16bits ×...
Page 304 DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In the SH7709S, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval.
Page 305 output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Page 306 CKIO A25-A0 Transfer source address Transfer destination address D31-D0 RD/WR DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 10.15 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode (16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Normal Memory)
Page 307 Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25 to A16, A15, A14, A11 to A0 CS2 or CS3 RAS3x CASx RD/WR DQMxx D31 to D0 Figure 10.16 Basic Timing for Synchronous DRAM Burst Read...
Page 308 Figure 10.17 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is asserted in each of cycles Td1–Td4 in a synchronous DRAM cycle.
Page 309 Single Read: Figure 10.18 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed.
Page 310 Burst Write: The timing chart for a burst write is shown in figure 10.19. In the SH7709S, a burst write occurs only in the event of cache write-back or 16-byte DMAC transfer. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto- precharge is issued in the Tc4 cycle.
Page 311 Wait state by WAIT signal input CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 WAIT Figure 10.19 Basic Timing for Synchronous DRAM Burst Write Single Write: The basic timing chart for write access is shown in figure 10.20. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle.
Page 312 (Trwl) (Tpc) CKIO Address upper bits A12 or A10 Address lower bits RD/WR RAS3x CASx DQMxx D31 to D0 Figure 10.20 Basic Timing for Synchronous DRAM Single Write...
Page 313 Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 314 A Tnop cycle, in which no operation is performed, is inserted before the Tc cycle in which the READ command is issued in figure 10.22, but when synchronous DRAM is read, there is a two- cycle latency for the DQMxx signal that performs the byte specification. If the Tc cycle were performed immediately, without inserting a Tnop cycle, it would not be possible to perform the DQMxx signal specification for Td1 cycle data output.
Page 315 Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.21 Burst Read Timing (No Precharge)
Page 316 Tnop Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.22 Burst Read Timing (Same Row Address)
Page 317 Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.23 Burst Read Timing (Different Row Addresses)
Page 318 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.24 Burst Write Timing (No Precharge)
Page 319 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.25 Burst Write Timing (Same Row Address)
Page 320 CKIO A25–A16, A13 (A25– A16, A11) A12 (A10) A15, A14, A11–A0 (A15–A12, A9–A0) CS2 or CS3 RAS3x CASx RD/WR DQMxx D31–D0 Figure 10.26 Burst Write Timing (Different Row Addresses)
Page 321 Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
Page 322 RTCNT cleared to 0 when RTCOR value RTCNT = RTCOR RTCNT H'00000000 Time ≠ 000 RTCSR.CKS(2–0) = 000 CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle Figure 10.27 Auto-Refresh Operation...
Page 323 TRrw TRrw CKIO RAS3U, RAS3L CASU, CASL RD/WR Figure 10.28 Synchronous DRAM Auto-Refresh Timing...
Page 324 After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the SH7709S’s standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared.
Page 325 (driven low). Therefore, normal refreshing can be performed by having the IRQOUT pin monitored by a bus master other than the SH7709S requesting the bus, or the bus arbiter, and returning the bus to the SH7709S. When refreshing is started, and if no other interrupt...
Page 326 To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by the SH7709S, arbitrary data is written in a byte-size access to the following addresses.
Page 327 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO A15 to A13 or A15 to A12 A12 or A10 A9 to A2 RD/WR RAS3U or RAS3L CASU or CASL D31 to D0 (High) Figure 10.30 Synchronous DRAM Mode Write Timing...
Page 328: Burst Rom Interface
10.3.5 Burst ROM Interface Setting bits A0BST1–0, A5BST1–0, and A6BST1–0 in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 10.31.
Page 329 CKIO A25 to A4 A3 to A0 RD/WR D31 to WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.31 Burst ROM Wait Access Timing...
Page 330 CKIO A25 to A4 A3 to A0 RD/WR D31 to D0 WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 10.32 Burst ROM Basic Access Timing...
Page 331: Pcmcia Interface
10.3.6 PCMCIA Interface In the SH7709S, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2.
Page 332 A24 to A0 A25 to A0 D15 to D0 D7 to D0 RD/WR CE1B/(CS6) D15 to D0 CE1A/(CS5) CE2B CE2A D15 to D8 PC card (memory/IO) SH7709S WE/PGM ICIORD (IORD) ICIOWR (IOWR) WAIT WAIT IOIS16 (IOIS16) Card CD1, CD2 detection...
Page 333 (CS5, CE2A, CS6, CE2B), and write data (D15–D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in the SH7709S). The SH7709S provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register.
Page 334 Tpcm1 Tpcm2 CKIO A25 to A0 CExx RD/WR (read) D15 to D0 (read) (write) D15 to D0 (read) Figure 10.34 Basic Timing for PCMCIA Memory Card Interface...
Page 335 Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR (read) D15 to D0 (read) (write) D15 to D0 (write) WAIT Figure 10.35 Wait Timing for PCMCIA Memory Card Interface...
Page 336 Memory Card Interface Burst Timing: In the SH7709S, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6.
Page 337 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 CExx RD/WR (read) D15 to D0 (read) WAIT Figure 10.37 Wait Timing for PCMCIA Memory Card Interface Burst Access...
Page 338 When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16 Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal.
Page 339 I/O Card Interface Timing: Figures 10.39 and 10.40 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed.
Page 340 Tpci1 Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) Figure 10.39 Basic Timing for PCMCIA I/O Card Interface...
Page 341 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) WAIT IOIS16 Figure 10.40 Wait Timing for PCMCIA I/O Card Interface...
Page 342 Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CKIO A25 to A1 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) WAIT IOIS16 Figure 10.41 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface...
Page 343: Waits Between Access Cycles
SH7709S performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles.
Page 344: Bus Arbitration
See Appendix A.1, Pin States, for the pin states when the bus is released. The SH7709S sometimes needs to retrieve a bus it has released. For example, when memory generates a refresh request or an interrupt request internally, the SH7709S must perform the appropriate processing.
Page 345: Bus Pull-Up
10.3.9 Bus Pull-Up With the SH7709S, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted. Figure 10.43 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by setting the PULD bit in BCR1 to 1.
Page 346 CKIO Pull-up Pull-up D31–D0 Figure 10.44 Pull-Up Timing for Pins D31 to D0 (Read Cycle) CKIO Pull-up Pull-up D31–D0 Figure 10.45 Pull-Up Timing for Pins D31 to D0 (Write Cycle)
Page 347: 10.3.10 Mcs[0] To Mcs[7] Pin Control
10.3.10 MCS[0] to MCS[7] Pin Control The SH7709S is provided with pins MCS[0]–MCS[7] as dedicated CS pins for the ROM connected to area 0 or 2. Assertion of MCS[0]–MCS[7] is controlled by settings in MCSCR0– MCSCR7. This enables 32-, 64-, 128-, or 256-Mbit memory to be connected to area 0 or area 2.
Page 348 Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7) MCS[x] Assertion Conditions MCSCRx Settings CS2/0 CAP1 CAP0 A25 Address Bus A [25:0] Notes — — — H'0000000 to H'1FFFFFF 256-Mbit ROM — — — H'2000000 to H'3FFFFFF — — H'0000000 to H'0FFFFFF 128-Mbit ROM —...
Page 349 Table 10.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7) (cont) MCS[x] Assertion Conditions MCSCRx Settings CS2/0 CAP1 CAP0 A25 Address Bus A[25:0] Notes — — — H'0000000 to H'1FFFFFF 256-Mbit ROM — — — H'2000000 to H'3FFFFFF — — H'0000000 to H'0FFFFFF 128-Mbit ROM —...
Page 350: Section 11 Direct Memory Access Controller (Dmac)
11.1 Overview The SH7709S includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (IrDA, SCIF, A/D converter, and D/A converter).
Page 351  Channel 3: In this channel, direct address mode or indirect address transfer mode can be specified. • Reload function: The value that was specified in the source address register can be automatically reloaded every four DMA transfers. This function is only available in channel 2. •...
Page 352: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the DMAC. DMAC module Iteration SARn control Register DARn control On-chip DMATCRn peripheral Start-up module control CHCRn DMAOR DREQ0, DREQ1 IrDA, SCIF Request A/D converter priority control DEIn DACK0, DACK1 DRAK0, DRAK1 External Bus interface...
Page 353: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the DMAC pins. Table 11.1 DMAC Pins Channel Name Symbol Function DREQ0 DMA transfer request DMA transfer request input from external device to channel 0 DMA transfer request DACK0 Strobe output to an external I/O upon acceptance DMA transfer request from external device to channel 0...
Page 354: Register Configuration
11.1.4 Register Configuration Table 11.2 summarizes the DMAC registers. The DMAC has a total of 17 registers: each channel has four registers, and one overall DMAC control register. Table 11.2 DMAC Registers Abbrevi- Register Access Channel Name ation R/W Initial Value Address Size Size DMA source address register 0...
Page 355 Table 11.2 DMAC Registers (cont) Abbrevi- Register Access Channel Name ation R/W Initial Value Address Size Size DMA source address register 3 SAR3 Undefined H'04000050 16, 32* (H'A4000050)* DMA destination address register 3 DAR3 Undefined H'04000054 16, 32* (H'A4000054)* DMA transfer count register 3 Undefined H'04000058 DMATCR3 R/W...
Page 356: Register Descriptions
11.2 Register Descriptions 11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address.
Page 357: Dma Destination Address Registers 0-3 (Dar0-Dar3)
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers include a count function, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address.
Page 358: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 24-bit readable/writable registers that specify the DMA transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is H'000001, and 16,777,216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining number of transfers.
Page 359: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that specify the operation mode, transfer method, etc., for each channel. Bit 20 is only used in CHCR3; it is not used in CHCR0 to CHCR2. Consequently, writing to this bit is invalid in CHCR0 to CHCR2;...
Page 360 Bits 31 to 21—Reserved: These bits are always read as 0. The write value should always be 0. Bit 20—Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in channel 3. This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if this bit is read.
Page 361 Bit 17—Acknowledge Mode Bit (AM): Specifies whether DACK is output in the data read cycle or in the data write cycle in dual address mode. DACK is always output in single address mode, regardless of this bit specification. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3;...
Page 362 Bits 13 and 12—Source Address Mode Bits 1 and 0 (SM1, SM0): Select whether the DMA source address is incremented, decremented, or left fixed. Bit 13: SM1 Bit 12: SM0 Description Fixed source address (Initial value) Source address is incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) Source address is decremented (–1 in 8-bit transfer, –2 in 16- bit transfer, –4 in 32-bit transfer;...
Page 363 Bits 11 to 8—Resource Select Bits 3 to 0 (RS3 to RS0): Specify which transfer requests will be sent to the DMAC. Bit 11: Bit 10: Bit 9: Bit 8: Description External request * , dual address mode (Initial value) Setting prohibited External request / Single address mode External address space →...
Page 364 Bit 6—DREQ Select Bit (DS): Selects low-level or falling-edge detection as the sampling method for the DREQ pin used in external request mode. This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and CHCR3;...
Page 365 Bit 1—Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1.
Page 366: Dma Operation Register (Dmaor)
11.2.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the DMAC transfer mode. These register values are initialized to 0 in a reset. The previous value is retained in standby mode. Bit: —...
Page 367 Bit 2—Address Error Flag Bit (AE): Indicates that an address error occurred by the DMAC. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description No DMAC address error;...
Page 368: Operation
11.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Page 369 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and AE, NMIF, TE = 0? Transfer request?* Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated AE = 1 or NMIF = 1 or DMATCR = 0?
Page 370: Dma Transfer Requests
11.3.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip module request.
Page 371 (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon input of a transfer request signal. The source of the transfer request does not have to be the data transfer source or destination.
Page 372: Channel Priority
11.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority order of the channels remain fixed.
Page 373 (1) When channel 0 transfers Initial priority order Channel 0 becomes lowest- CH0 > CH1 > CH2 > CH3 priority. Priority order CH1 > CH2 > CH3 > CH0 after transfer (2) When channel 1 transfers Channel 1 becomes lowest- Initial priority order CH0 >...
Page 374 Figure 11.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously for channels 0 and 3. 2.
Page 375: Dma Transfer Types
11.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 11.5. Dual address mode has a direct address mode and indirect address mode. In direct address mode, an output address value is the data transfer target address; in indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address.
Page 376 (1) In direct address transfer mode, DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 11.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle.
Page 377 CKIO Transfer source Transfer destination A25 to A0 address address D31 to D0 DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) (2) In indirect address transfer mode, the address of memory in which data to be transferred is...
Page 378 SAR3 Memory DAR3 Transfer source module Temporary buffer Transfer destination Data buffer module When the value in SAR3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address.
Page 379 CKIO Transfer Transfer Transfer Indirect A25 to A0 source source destination address address (H) address (L) address Indirect Indirect Transfer Transfer D31 to D0 address (H) address (L) data data Internal Transfer source Indirect address address ∗ address Internal Transfer Transfer Transfer source address ∗...
Page 380 DACK shown in figure 11.9, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus External data bus SH7709S External DMAC memory External device...
Page 381 CKIO Address output to external memory space A25 to A0 Write strobe signal to external memory space D31 to D0 Data output from external device with DACK DACKn DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CKIO Address output to external memory space...
Page 382 CKIO A25 to A0 Transfer source address D31 to D0 DACKn Figure 11.11 Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer, External Memory Space (Ordinary Memory) → External Device with DACK) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR0–CHCR3.
Page 383 DREQ Bus returned to CPU Bus cycle DMAC DMAC CPU DMAC DMAC CPU Read Write Read Write Figure 11.12 Example of DMA Transfer in Cycle-Steal Mode • Burst Mode Once the bus is obtained, the transfer is performed continuously until the transfer end condition is satisfied.
Page 384 Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 11.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.6 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Request Transfer Usable...
Page 385 Bus Mode and Channel Priority Order: When, for example, channel 1 is transferring in burst mode and there is a transfer request to channel 0, which has higher priority, the channel 0 transfer will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle-steal mode or burst mode.
Page 386: Number Of Bus Cycle States And Dreq Pin Sampling Timing
Number of Bus Cycle States and DREQ Pin Sampling Timing 11.3.5 Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 10, Bus State Controller (BSC).
Page 387 For example, in figure 11.20, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. Subsequent sampling operations are performed in the idle cycle following the end of the DMA transfer cycle.
Page 388 Figure 11.15 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)
Page 389 Figure 11.16 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)
Page 390 Figure 11.17 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles)
Page 391 Figure 11.18 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed)
Page 392 Figure 11.19 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)
Page 393 Figure 11.20 Burst Mode, Level Input...
Page 394 Figure 11.21 Burst Mode, Edge Input...
Page 395: Source Address Reload Function
11.3.6 Source Address Reload Function Channel 2 includes a reload function, in which the value is returned to the value set in the source address register (SAR2) every four transfers by setting the RO bit in CHCR2 to 1. 16-byte transfer cannot be used.
Page 396 Internal SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2 SAR2 address bus Internal SAR2 data SAR2+2 data SAR2+4 data SAR2+6 data data bus First transfer on channel 2 Second transfer Third transfer Fourth transfer Fifth transfer SAR2 output SAR2+2 output SAR2+4 output SAR2+6 output DAR2 output...
Page 397: Dma Transfer Ending Conditions
11.3.7 DMA Transfer Ending Conditions The DMA transfer ending conditions are different for ending on an individual channel and ending on all channels together. At the end of transfer, the following conditions are applied except in the case where the value set in the DMA transfer count register (DMATCR) reaches 0. (a) Cycle-steal mode (external request, internal request, and auto-request) When the transfer ending conditions are satisfied, DMAC transfer request acceptance is suspended.
Page 398 Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit in the channel’s CHCR register is cleared to 0. • When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR.
Page 399: Compare Match Timer (Cmt)
11.4 Compare Match Timer (CMT) 11.4.1 Overview The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The CMT has a 16-bit counter. Features The CMT has the following features: • Four types of counter input clock can be selected ...
Page 400: Register Descriptions
Register Configuration Table 11.7 summarizes the CMT register configuration. Table 11.7 Register Configuration Initial Access Size Name Abbreviation Value Address (Bits) Compare match timer start CMSTR R/(W) H'0000 H'04000070 8, 16, 32 register (H'A4000070)* Compare match timer CMCSR0 R/(W)* H'0000 H'04000072 8, 16, 32 control/status register 0...
Page 401 Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0. Bit 0: STR0 Description CMCNT0 count operation halted (Initial value) CMCNT0 count operation Compare Match Timer Control/Status Register 0 (CMCSR0) The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation.
Page 402 Bit 6—Reserved: This bit can be read or written. The wite value should always be 0. Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the clock input to CMCNT from among the four internal clocks obtained by dividing the system clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the clock selected by CKS1 and CKS0.
Page 403: Operation
Compare Match Constant Register 0 (CMCOR0) Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare match period. CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode. Bit: Initial value: R/W: Bit:...
Page 404: Compare Match
CMCNT0 Count Timing One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the Pφ clock can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 11.26 shows the timing. Internal clock CMCNT0 input clock CMCNT0 Figure 11.26 Count Timing 11.4.4 Compare Match Compare Match Flag Setting Timing...
Page 405 CMCNT0 input clock CMCNT0 CMCOR0 Compare match signal Figure 11.27 CMF Setting Timing Compare Match Flag Clearing Timing The CMF bit in the CMCSR0 register is cleared by writing 0 to it after reading 1. Figure 11.28 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle Figure 11.28 Timing of CMF Clearing by the CPU...
Page 406: Examples Of Use
11.5 Examples of Use 11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory In this example, receive data of the on-chip IrDA is transferred to external memory using DMAC channel 3. Table 11.8 shows the transfer conditions and register settings. In addition, it is recommended that the trigger for the number of receive FIFO data bytes in IrDA be set to 1 (RTRG1 = RTRG0 = 0 in SCFCR).
Page 407: Example Of Dma Transfer Between A/D Converter And External Memory
11.5.2 Example of DMA Transfer between A/D Converter and External Memory In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with the address reload function on. Table 11.9 shows the transfer conditions and register settings. Table 11.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D Converter and External Memory Transfer Conditions...
Page 408: Example Of Dma Transfer Between External Memory And Scif Transmitter (Indirect Address On)
As a result, the values in the DMAC are as shown in table 11.10 when the fourth transfer ends, depending on whether the address reload function is on or off. Table 11.10 Values in DMAC after End of Fourth Transfer Items Address reload on Address reload off...
Page 409 Table 11.11 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Register Setting Transfer source: External memory SAR3 H'00400000 Value stored in address H'00400000 — H'00450000 Value stored in address H'04500000 — H'55 Transfer destination: On-chip SCIF TDR2 DAR3 H'04000156 Number of transfers: 10...
Page 410: Usage Notes
11.6 Usage Notes 1. The DMA channel control registers (CHCR0–CHCR3) can be accessed with any data size. The DMA operation register (DMAOR) must be accessed by byte (8 bits) or word (16 bits); other registers must be accessed by word (16 bits) or longword (32 bits). 2.
Page 412: Section 12 Timer (Tmu)
• All channels can operate when the SH7709S is in standby mode: When the RTC output clock is being used as the counter input clock, the SH7709S is still able to count in standby mode. • Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read.
Page 413: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. Bus interface Prescaler Pφ TOCR TCLK Clock controller RTCCLK TSTR Ch. 0 TCR0 Counter controller TCNT0 TCOR0 Interrupt TUNI0 controller Ch. 1 TCR1 Counter controller TCNT1 TCOR1 Interrupt TUNI1 controller Ch.
Page 414: Pin Configuration
12.1.3 Pin Configuration Table 12.1 shows the pin configuration of the TMU. Table 12.1 TMU Pin Channel Description Clock input/clock output TCLK I/O External clock input pin/input capture control input pin/realtime clock (RTC) output pin 12.1.4 Register Configuration Table 12.2 shows the TMU register configuration. Table 12.2 TMU Registers Access Channel...
Page 415: Tmu Registers
12.2 TMU Registers 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock.
Page 416: Timer Control Registers (Tcr)
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0. Bit 2—Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2). Bit 2: STR2 Description TCNT2 count halted (Initial value) TCNT2 counts Bit 1—Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
Page 417 Channel 0 and 1 TCR Bit Configuration: Bit: — — — — — — — Initial value: R/W: Bit: — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W: Channel 2 TCR Bit Configuration: Bit: — — — — —...
Page 418 Bit 8—Underflow Flag (UNF): Status flag that indicates occurrence of a TCNT underflow. Bit 8: UNF Description TCNT has not underflowed Clearing condition: When 0 is written to UNF (Initial value) TCNT has underflowed Setting condition: When TCNT underflows* Note: * Contents do not change when 1 is written to UNF. Bits 7 and 6—Input Capture Control (ICPE1, ICPE0): A function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts.
Page 419 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): Select the external clock edge when the external clock is selected, or when the input capture function is used. Bit 4: CKEG1 Bit 3: CKEG0 Description Count/capture register set on rising edge (Initial value) Count/capture register set on falling edge Count/capture register set on both rising and falling edge...
Page 420: Timer Constant Registers (Tcor)
12.2.4 Timer Constant Registers (TCOR) The TMU has three TCOR registers, one for each channel. TCOR specifies the value for setting in TCNT when a TCNT count-down results in an under flow. TCOR is a 32-bit readable/writable register. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and retains its contents, in standby mode.
Page 421 Because the internal bus for the SH7709S on-chip peripheral modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
Page 422: Input Capture Register (Tcpr2)
12.2.6 Input Capture Register (TCPR2) Input capture register 2 (TCPR2) is a read-only 32-bit register provided only in timer 2. Control of TCPR2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE0 and CKEG1/CKEG0) in TCR2. When a TCPR2 setting indication due to the TCLK pin occurs, the value of TCNT2 is copied into TCPR2.
Page 423: Tmu Operation
12.3 TMU Operation Each of three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). TCNT counts down. The auto-reload function enables cycle counting and counting by external events. Channel 2 has an input capture function. 12.3.1 General Operation When the STR0–STR2 bits in the timer start register (TSTR) are set to 1, the corresponding timer...
Page 424 Select operation Select counter clock Set underflow interrupt generation When using input capture function Set interrupt generation Set timer constant register Initialize timer counter Start counting Note: When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
Page 425 Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time STR0–STR2 Figure 12.3 Auto-Reload Count Operation TCNT Count Timing: • Internal Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select whether peripheral module clock Pφ...
Page 426: Input Capture Function
• External Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rising, falling, or both edges may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges.
Page 427: Interrupts
TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time TCLK TCPR2 Set TCNT value ICPI Figure 12.7 Operation Timing when Using Input Capture Function (Using TCLK Rising Edge) 12.4 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2).
Page 428: Status Flag Clearing Timing
12.4.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. TCR write cycle Pφ Peripheral address bus TCR address UNF, ICPF Figure 12.9 Status Flag Clearing Timing 12.4.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel.
Page 429: Usage Notes
12.5 Usage Notes 12.5.1 Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2–STR0) in the timer start register (TSTR) to halt timer counting. 12.5.2 Reading Registers Synchronization processing is performed for timer counting during register reads.
Page 430: Section 13 Realtime Clock (Rtc)
Section 13 Realtime Clock (RTC) 13.1 Overview The SH7709S has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. 13.1.1 Features • Clock and calendar functions (BCD display): Seconds, minutes, hours, date, day of the week, month, and year •...
Page 431: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the RTC. Externally connected circuit EXTAL2 second Reset 128 Hz Oscillator circuit XTAL2 R64CNT 32.768 kHz interface RSECCNT Prescaler RMINCNT (÷ 2) RHRCNT 16.384 kHz RTCCLK RWKCNT RDAYCNT Prescaler (÷ 128) RMONCNT RYRCNT Interrupt...
Page 432: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the RTC pin configuration. Table 13.1 RTC Pins Signal Name Description RTC oscillator crystal pin EXTAL2 Connects crystal to RTC oscillator* RTC oscillator crystal pin XTAL2 Connects crystal to RTC oscillator* Clock input/clock output TCLK External clock input pin/input capture control input pin/realtime clock (RTC)
Page 433: Rtc Register Configuration
13.1.4 RTC Register Configuration Table 13.2 shows the RTC register configuration. Table 13.2 RTC Registers Name Abbreviation R/W Initial Value Address Access Size 64-Hz counter R64CNT Undefined H'FFFFFEC0 Second counter RSECCNT Undefined H'FFFFFEC2 Minute counter RMINCNT Undefined H'FFFFFEC4 Hour counter RHRCNT Undefined H'FFFFFEC6...
Page 434: Rtc Registers
13.2 RTC Registers 13.2.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the states of the RTC divider circuit, RTC prescaler, and R64CNT between 64 Hz and 1 Hz. R64CNT is initialized to H'00 by setting the RESET bit in RTC control register 2 (RCR2) or the ADJ bit in RCR2 to 1.
Page 435: Minute Counter (Rmincnt)
13.2.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range that can be set is 00–59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
Page 436: Day Of Week Counter (Rwkcnt)
13.2.5 Day of Week Counter (RWKCNT) The day of week counter (RWKCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range that can be set is 0–6 (decimal).
Page 437: Date Counter (Rdaycnt)
13.2.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range that can be set is 01–31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2.
Page 438: Year Counter (Ryrcnt)
13.2.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range that can be set is 00–99 (decimal).
Page 439: Minute Alarm Register (Rminar)
13.2.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 440: Day Of Week Alarm Register (Rwkar)
13.2.12 Day of Week Alarm Register (RWKAR) The day of week alarm register (RWKAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 441: Date Alarm Register (Rdayar)
13.2.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 442: Rtc Control Register 1 (Rcr1)
13.2.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit readable/writable register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset or a manual reset.
Page 443: Rtc Control Register 2 (Rcr2)
Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. Bit 3: AIE Description An alarm interrupt is not generated when the AF flag is set to 1 (Initial value) An alarm interrupt is generated when the AF flag is set to 1 Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time.
Page 444 Bits 6 to 4—Periodic Interrupt Flags (PES2-PES0): Specify the periodic interrupt. Bit 6: PES2 Bit 5: PES1 Bit 4: PES0 Description No periodic interrupts generated (Initial value) Periodic interrupt generated every 1/256 second Periodic interrupt generated every 1/64 second Periodic interrupt generated every 1/16 second Periodic interrupt generated every 1/4 second Periodic interrupt generated every 1/2 second Periodic interrupt generated every 1 second...
Page 445: Rtc Operation
Bit 0—Start Bit (START): Halts and restarts the counter (clock). Bit 0: START Description Second/minute/hour/day/week/month/year counter halts Second/minute/hour/day/week/month/year counter runs normally (Initial value) Note: The 64-Hz counter always runs unless stopped with the RTCEN bit. 13.3 RTC Operation 13.3.1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on.
Page 446: Reading The Time
13.3.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts;...
Page 447: Alarm Function
13.3.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) to 1 in the register to which the alarm applies, and then set the alarm time in the lower bits.
Page 448: Crystal Oscillator Circuit
13.5. Table 13.5 Recommended Oscillator Circuit Constants (Recommended Values) fosc Cout 32.768 kHz 10 to 22 pF 10 to 22 pF SH7709S EXTAL2 XTAL2 XTAL Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc.
Page 449: Usage Notes
13.4 Usage Notes 13.4.1 Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 13.4.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 13.6.
Page 450: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) 14.1 Overview The SH7709S has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. The SCI supports a smart card interface, which is a serial communication feature for IC card interfaces that conforms to the ISO/IEC standard 7816-3 for identification cards.
Page 451: Block Diagram
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive- error interrupts are requested independently. • When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power. 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the SCI.
Page 452 Figures 14.2, 14.3, and 14.4 show block diagrams of the SCI I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
Page 453 Reset SCP0MD0 Internal data bus PCRW Reset SCP0MD1 PCRW Reset SCPT[0]/TxD0 SCP0DT1 PDRW Output enable Serial transmission output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 14.3 SCPT[0]/TxD0 Pin...
Page 454: Pin Configuration
SCPT[0]/RxD0 Serial receive data Internal data bus PDRR* Legend PDRR: PDR read Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 14.4 SCPT[0]/RxD0 Pin 14.1.3 Pin Configuration The SCI has the serial pins summarized in table 14.1. Table 14.1 SCI Pins Pin Name Abbreviation...
Page 455: Register Configuration
14.1.4 Register Configuration Table 14.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 14.2 SCI Registers Name Abbreviation Initial Value Address Access size Serial mode register...
Page 456: Receive Data Register (Scrdr)
14.2.2 Receive Data Register (SCRDR) The receive data register (SCRDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCRDR for storage. SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously.
Page 457: Transmit Data Register (Sctdr)
14.2.4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in SCTDR into SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in SCTDR during serial transmission from SCTSR.
Page 458 Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 8-bit data (Initial value) 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not transmitted.
Page 459 Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character.
Page 460: Serial Control Register (Scscr)
14.2.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a reset and in standby or module standby mode.
Page 461 Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description Transmitter disabled* (Initial value) Transmitter enabled* Notes: *1 The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is fixed at 1. *2 Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR.
Page 462 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Page 463 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0).
Page 464: Serial Status Register (Scssr)
14.2.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE, RDRF, ORER, PER, and FER).
Page 465 Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data. Bit 6: RDRF Description SCRDR does not contain valid receive data (Initial value) [Clearing conditions] (1) RDRF is cleared to 0 when the chip is reset or enters standby mode. (2) Software reads RDRF after it has been set to 1, then writes 0 in RDRF.
Page 466 Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in asynchronous mode. Bit 4: FER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) FER is cleared to 0 when the chip is reset or enters standby mode. (2) When software reads FER after it has been set to 1, then writes 0 to FER.
Page 467 Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written to. Bit 2: TEND Description Transmission is in progress [Clearing condition] TEND is cleared to 0 when software reads TDRE after it has been set to 1, then...
Page 468: Sc Port Control Register (Scpcr)/Sc Port Data Register (Scpdr)
14.2.8 SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR) The SC port control register (SCPCR) and SC port data register (SCPDR) control I/O and data for the port pins multiplexed with the serial communication interface (SCI) pins. SCPCR settings are used to perform I/O control, to enable data written in SCPDR to be output to the TxD pin, and input data to be read from the RxD pin, and to control serial transmission/reception breaks.
Page 469 SCPDR Bit 1—Serial Clock Port Data (SCP1DT): Specifies the serial port SCK pin I/O data. Input or output is specified by the SCP1MD1 and SCP1MD0 bits. In output mode, the value of the SCP1DT bit is output to the SCK pin. Bit 1: SCP1DT Description...
Page 470: Bit Rate Register (Scbrr)
14.2.9 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR.
Page 471 Table 14.4 lists examples of SCBRR settings in asynchronous mode, and table 14.5 lists examples of SCBRR settings in synchronous mode. Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 2.097152 2.4576 Bit Rate (bits/s) n Error (%) n Error (%) n Error (%) 0.03...
Page 472 Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode (cont) Pφ (MHz) 4.9152 Bit Rate (bits/s) n Error (%) n Error (%) n Error (%) 0.31 –0.25 –0.44 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 0.16 1200 0.00 0.16 0.16 2400...
Page 473 Table 14.4 Bit Rates and SCBRR Settings in Asynchronous Mode (cont) Pφ (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16...
Page 474 Table 14.5 Bit Rates and SCBRR Settings in Synchronous Mode Pφ (MHz) 28.7 Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5k 100k 250k — — 500k — — — — —...
Page 475 Table 14.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 14.7 and 14.8 list the maximum rates for external clock input. Table 14.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ...
Page 476 Table 14.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 2.0000 125000 9.8304 2.4576...
Page 477: Operation
14.3 Operation 14.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous/synchronous mode and the transmission format are selected in the serial mode register (SCSMR), as shown in table 14.9.
Page 478 Table 14.9 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit STOP Mode Length cessor Bit Length Asynchronous 8-bit Not set Not set 1 bit 2 bits...
Page 479: Operation In Asynchronous Mode
14.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 480 Transmit/Receive Formats: Table 14.11 lists the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 14.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits Serial Transmit/Receive Format and Frame Length CHR PE STOP 1 START...
Page 481 When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit.
Page 482 Initialization Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select communication format in SCSMR Set value in SCBRR Wait Has a 1-bit interval elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 483 Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Read TEND bit in SCSSR TEND = 1? Break output? Set SCPDR and SCPCR Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 484 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR into the transmit shift register (SCTSR).
Page 485 Figure 14.9 shows an example of SCI transmit operation in asynchronous mode. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDRE TEND TXI interrupt TXI interrupt TXI interrupt TEI interrupt request handler writes request request generated data to SCTDR generated...
Page 486 Start of reception Read ORER, PER, and FER bits in SCSSR PER ∨ FER ∨ ORER = 1? Read RDRF bit in SCSSR Error handling RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception...
Page 487 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER bits in SCSSR to 0 Figure 14.10 Sample Flowchart for Receiving Serial Data (cont)
Page 488 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. 3.
Page 489: Multiprocessor Communication
Figure 14.11 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Serial Idle (mark) data state RDRF RXI interrupt request generated 1 frame RXI interrupt handler ERI interrupt reads data and clears request generated RDRF bit to 0 by framing error...
Page 490 Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmit cycle: Data transmit cycle: specifies receiving station data transmission to...
Page 491 Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 Transmission ended? Read TEND bit in SCSSR TEND = 1? Break output? Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 492 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data, and transfers this data from SCTDR into the transmit shift register (SCTSR).
Page 493 Multi- Multi- processor processor Start Stop Stop Start Data Data Serial Idle (mark) data state TDRE TEND TXI interrupt Writes data to TDR TXI interrupt TEI interrupt request with the TXI interrupt request request generated processing routine generated generated and clears TDRE bit to 0 1 frame Figure 14.14 Example of SCI Multiprocessor Transmit Operation...
Page 494 Start of reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? Read RDRF bit in SCSSR RDRF = 1? Read receive data from SCRDR Is ID the station’s ID? Read ORER and FER bits in SSCSR...
Page 495 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR to 0 Clear ORER and FER bits in SCSSR to 0 Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Page 496 Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. Data Data Start Stop Start Stop (ID1) (data 1) Serial Idle (mark) data state MPIE RDRF value RXI interrupt request RXI interrupt handler ID is not station’s No RXI interrupt (multiprocessor interrupt) reads RDR data and...
Page 497 Data Data Start Stop Stop Start (ID2) (Data 2) Serial Idle (mark) data state MPIE RDRF Data2 value RXI interrupt request RXI interrupt handler ID is that of station, MPIE bit (multiprocessor reads RDR data and so reception continues set to 1 interrupt) generated, clears RDRF bit to 0 unchanged and data...
Page 498: Synchronous Operation
14.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress.
Page 499 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR).
Page 500 Initialization Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) Set transmit/receive format in SCSMR Set value in SCBRR Wait Has a 1-bit period elapsed? Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 501 Start of transmission Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Read TEND bit in SCSSR TEND = 1? Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 502 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (SCTDR) contains new data and loads this data from SCTDR into the transmit shift register (SCTSR).
Page 503 Receiving Serial Data (Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
Page 504 Start of reception Read ORER bit in SCSSR ORER = 1? Read RDRF bit in SCSSR Error handling RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 505 Error handling ORER = 1? Overrun error handling Clear ORER bit in SCSSR to 0 Figure 14.21 Sample Flowchart for Receiving Serial Data (cont) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2.
Page 506 Transfer direction Serial clock Serial Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data RDRF ORER ERI interrupt RXI interrupt RXI interrupt RXI interrupt request generated request request handler reads data by overrun error generated generated and clears RDRF...
Page 507 Start of transmission/reception Read TDRE bit in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR ORER = 1? Error processing Read RDRF bit in SCSSR RDRF = 1? Read receive data from SCRDR and clear RDRF bit in SCSSR to 0 All data...
Page 508: Sci Interrupts
14.4 SCI Interrupts The SCI has four interrupt sources transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.13 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCSCR).
Page 509: Usage Notes
14.5 Usage Notes Note the following points when using the SCI. SCTDR Writing and TDRE Flag: The TDRE bit in the serial status register (SCSSR) is a status flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when it transfers data from SCTDR to SCTSR.
Page 510 TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally.
Page 511 The receive margin in asynchronous mode can therefore be expressed as in equation 1. Equation 1: D – 0.5 (1 + F) × 100% M = 0.5 – – (L – 0.5)F – M = Receive margin (%) Where: N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0 to 1.0) L = Frame length (L = 9 to 12) F = Absolute deviation of clock frequency...
Page 512: Section 15 Smart Card Interface
Section 15 Smart Card Interface 15.1 Overview As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC7816-3 (Identification Card) standard. Register settings are used to switch between the normal serial communication interface and the smart card interface.
Page 513: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCBRR SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Baud rate Pφ generator Pφ/4 SCRSR SCTSR Transmit/ receive Pφ/16 control Pφ/64 Clock Parity generation Parity check External clock...
Page 514: Pin Configuration
15.1.3 Pin Configuration Table 15.1 summarizes the smart card interface pins. Table 15.1 Smart Card Interface Pins Pin Name Abbreviation I/O Function Serial clock pin SCK0 Output Clock output Receive data pin RxD0 Input Receive data input Transmit data pin TxD0 Output Transmit data output...
Page 515: Register Descriptions
15.2 Register Descriptions This section describes the registers added for the smart card interface and the bits whose functions are changed. 15.2.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart card interface functions.
Page 516: Serial Status Register (Scssr)
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function. Bit 0 : SMIF Description Smart card interface function disabled (Initial value) Smart card interface function enabled 15.2.2 Serial Status Register (SCSSR) In smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for bit 2, the TEND bit, are also changed.
Page 517: Operation
Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. Bit 2: TEND Description Transmission is in progress...
Page 518: Pin Connections
15.3.2 Pin Connections Figure 15.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply side with a register.
Page 519: Data Format
15.3.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, error signals are sampled and data re-transmitted whenever an error signal is detected.
Page 520: Register Settings
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.3.4 Register Settings Table 15.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value.
Page 521: Clock
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. Parity is even (from the smart card standard), and so the parity bit is 0, which corresponds to state Z. Only data bits D7–D0 are inverted by the SINV bit.
Page 522 Table 15.4 Relationship of n to CKS1 and CKS0 CKS1 CKS0 Table 15.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n = 0) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5 4800.0 6720.4...
Page 523 Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) φ (MHz) Maximum Bit Rate (Bits/s) 7.1424 9600 10.00 13441 10.7136 14400 13.00 17473 14.2848 19200 16.00 21505 18.00 24194 The bit rate error is found as follows: φ P ×...
Page 524: Data Transmission And Reception
15.3.6 Data Transmission and Reception Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 15.5 shows a flowchart of the initialization process. 1.
Page 525 Initialization Clear TE and RE bits in SCSCR to 0 Clear FER/ERS, PER and ORER flags in SCSSR to 0 Set parity in O/E bit, set clock in CKS1 and CKS0 bits, and set C/A, in SCSMR Set SMIF, SDIR, and SINV bits in SCSMR Set value in SCBRR Set clock in CKE1 and CKE0 bits,...
Page 526 Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. This results in the transmission processing flowchart shown in figure 15.6. 1.
Page 527 Start Initialize Start of transmission FER/ERS = 0? Error handling TEND = 1? Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit in SCSCR to 0 End of transmission Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 528 Serial Data Reception: The processing procedures in smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 15.7. 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2.
Page 529 Start Initialize Start of reception ORER = 0 or PER = 0? Error handling RDRF = 1? Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Note: Numbers in parentheses refer to steps in the preceding procedure description.
Page 530: Usage Notes
Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization, clearing RE to 0, and setting TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization, clearing TE to 0, and setting RE to 1.
Page 531 372 clock cycles 186 clock cycles 371 0 371 0 Base clock Start Receive data (RxD) Synchro- nization sampling timing Data sampling timing Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: D –...
Page 532: Retransmission (Receive And Transmit Modes)
15.4.2 Retransmission (Receive and Transmit Modes) Retransmission when SCI is in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1.
Page 533 Retransmission when SCI is in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested.
Page 534: Section 16 Serial Communication Interface With Fifo (Scif)
(SCIF) 16.1 Overview The SH7709S has a two-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception that enable the SH7709S to perform efficient high-speed continuous communication.
Page 535: Block Diagram
16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Internal Module data bus data bus SCPCR SCFRDR2 SCFTDR2 SCFDR SCBRR SCFDR2 SCFCR2 stages) stages) SCSSR2 SCSCR2 Baud rate Pφ generator SCSMR2 Pφ/4 SCRSR SCTSR Transmit/ Pφ/16 receive control Pφ/64 Clock...
Page 536 Figures 16.2 to 16.4 show the SCIF I/O port pins. SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
Page 537 Reset SCP4MD0 Internal data bus PCRW Reset SCP4MD1 PCRW Reset SCPT[4]/TxD2 SCP4DT1 SCIF PDRW Output enable Serial transmission output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 16.3 SCPT[4]/TxD2 Pin...
Page 538: Pin Configuration
SCIF SCPT[4]/RxD2 Serial receive data Internal data bus PDRR* Legend PDRR: SCPDR read Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCPT[4]/RxD2 Pin 16.1.3 Pin Configuration The SCIF has the serial pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Abbreviation...
Page 539: Register Configuration
16.1.4 Register Configuration Table 16.2 summarizes the SCIF internal registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 16.2 SCIF Registers Register Name Abbreviation R/W Initial Value Address Access size Serial mode register 2 SCSMR2 H'00 H'04000150...
Page 540: Register Descriptions
16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
Page 541: Transmit Fifo Data Register (Scftdr)
16.2.4 Transmit FIFO Data Register (SCFTDR) The transmit FIFO data register (SCFTDR) is a 16-byte 8-bit-length FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR.
Page 542 Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data. Bit 5: PE Description Parity bit not added or checked (Initial value) Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting.
Page 543: Serial Control Register (Scscr)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on- chip baud rate generator. According to the setting of the CKS1 and CKS0 bits four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.2.8, Bit Rate Register (SCBRR).
Page 544 Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when serial receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in the receive FIFO register becomes more than the specified receive trigger number, and when the RDRF flag in SCSSR is set to1.
Page 545: Serial Status Register (Scssr)
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 = 0).
Page 546 Bit 7—Receive Error (ER): Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. Bit 7: ER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] (1) By a power-on reset or in standby mode ER is cleared to 0 when the chip is reset or enters standby mode (2) When 0 is written after 1 is read from ER.
Page 547 Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled.
Page 548 Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data register (SCFRDR). Bit 3: FER Description No receive framing error occurred in the data read from SCFRDR (Initial value) [Clearing conditions] (1) When the chip undergoes a power-on reset or enters standby mode. (2) When no framing error is present in the data read from SCFRDR.
Page 549 Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR).
Page 550: Bit Rate Register (Scbrr)
Upper 8 bits: PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: R/W: Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
Page 551 Table 16.3 SCSMR Settings SCSMR Settings Clock Source CKS1 CKS0 Pφ Pφ/4 Pφ/16 Pφ/64 Note: The bit rate error is given by the following formula: Pø × 10 × 100 Error (%) = – 1 (N+1) × 64 × 2 ×...
Page 552 Table 16.4 Bit Rates and SCBRR Settings (cont) Pφ (MHz) 3.6864 Bit Rate (bits/s) n Error (%) n Error (%) n Error (%) 0.03 0.70 0.03 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16...
Page 553 Table 16.4 Bit Rates and SCBRR Settings (cont) Pφ (MHz) 6.144 7.3728 Bit Rate (bits/s) n Error (%) n Error (%) n Error (%) 0.08 –0.07 0.03 0.00 0.00 0.16 0.00 0.00 0.16 0.00 0.00 0.16 1200 0.00 0.00 0.16 2400 0.00 0.00...
Page 554 Table 16.4 Bit Rates and SCBRR Settings (cont) Pφ (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00 0.16...
Page 555 Table 16.4 Bit Rates and SCBRR Settings (cont) Pφ (MHz) 24.576 28.7 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 0.31 0.13 0.16 0.00 0.46 –0.35 0.16 0.00 –0.08 0.16 0.16 0.00 0.46 –0.35 1200 0.16 0.00 –0.08 0.16 2400 0.16 0.00...
Page 556 Table 16.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.6 list the maximum rates for external clock input. Table 16.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ...
Page 557 Table 16.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 2.0000 125000 9.8304 2.4576...
Page 558: Fifo Control Register (Scfcr)
16.2.9 FIFO Control Register (SCFCR) Bit: RTRG1 RTRG0 TTRG1 TTRG0 TFRST RFRST LOOP Initial value: R/W: The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU.
Page 559 Bit 3—Modem Control Enable (MCE): Enables modem control signals CTS and RTS. Bit 3: MCE Description Modem signal disabled* (Initial value) Modem signal enabled Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Bit 2—Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit FIFO data register and resets the data to the empty state.
Page 560: Fifo Data Count Register (Scfdr)
16.2.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits.
Page 561: Operation
16.3 Operation 16.3.1 Overview For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication.
Page 562: Serial Operation
Table 16.8 SCSCR Settings and SCIF Clock Source Selection SCSCR Settings SCIF Transmit/Receive Clock Bit 1 Bit 0 Mode CKE1 CKE0 Clock Source SCK Pin Function Asynchronous Internal SCIF does not use the SCK pin mode Outputs a clock with a frequency 16 times the bit rate External Inputs a clock with frequency 16 times the...
Page 563 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR) (table 16.8). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Page 564 Initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE and RE bits cleared to 0) Set communication format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Set RTRG1-0, TTRG1-0, and MCE...
Page 565 • Serial data transmission Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data write: Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND flags, then clear these flags to 0.
Page 566 Start of transmission Read TDFE bit in SCSSR TDFE= 1? Write transmit data (16 - transmit trigger set number) to SCFTDR, read 1 from TDFE bit and TEND flag in SCSSR, then clear to 0 All data transmitted? Read TEND bit in SCSSR TEND= 1? Break output? Set SCPDR and SCPCR...
Page 567 In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR.
Page 568 Figure 16.7 shows an example of the operation for transmission. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) data state TDFE TEND TXI interrupt Data written to TXI interrupt request SCFTDR and TDFE request flag read as 1 then cleared to 0 by TXI interrupt handler One frame...
Page 569 • Serial data reception Figures 16.9 and 16.10 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0.
Page 570 Start of reception Read ORER, PER, FER flags in SCSSR PER v FER v ORER = 1? Error handling Read RDF flag in SCSSR RDF = 1? Read receive data from SCFRDR, and clear RDF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception...
Page 571 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. 2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set.
Page 572 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Page 573 Figure 16.11 shows an example of the operation for reception. Start Parity Stop Parity Stop Start Data Data Serial Idle (mark) D 0 D 1 D 7 0/1 data state RXI interrupt request One frame Data read and RDF ERI interrupt flag read as 1 then request generated cleared to 0 by...
Page 574: Scif Interrupts
16.4 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.10 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources.
Page 575: Usage Notes
16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR Writing and TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR).
Page 576 5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally.
Page 577 Equation 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. 7. Note on Use of Modem Signals: The following bug may occur when modem signals are used by the SCIF (serial communication interface with FIFO) (i.e.
Page 578: Section 17 Irda
Section 17 IrDA 17.1 Overview The SH7709S has an on-chip Infrared Data Association (IrDA) interface which is based on the IrDA 1.0 system and can perform infrared communication. It also can be used as the SCIF by making register settings.
Page 579: Block Diagram
17.1.2 Block Diagram Figure 17.1 shows a block diagram of the IrDA. Clock input TxD1 Modulation unit Transfer clock SCIF Demodulation unit RxD1 IrDA Switching IrDA/SCIF Legend SCIF: Serial communication interface with FIFO Figure 17.1 Block Diagram of IrDA...
Page 580 Figures 17.2 to 17.4 show the IrDA I/O port pins. SCIF pin I/O and data control is performed by bits 7 to 4 of SCPCR and bits 3 and 2 of SCPDR. For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR).
Page 581 Reset SCP2MD0 Internal data bus PCRW Reset SCP2MD1 PCRW Reset SCPT[2]/TxD1 SCP2DT1 IrDA PDRW Output enable Serial transfer output Legend PCRW: SCPCR write PDRW: SCPDR write Figure 17.3 SCPT[2]/TxD1 Pin...
Page 582: Pin Configuration
IrDA SCPT[2]/RxD1 Serial receive data Internal data bus PDRR * Legend PDRR: SCPDR read Note: * When reading the RxD1 pin, set the RE bit in SCSCR to 1. Figure 17.4 SCPT[2]/RxD1 Pin 17.1.3 Pin Configuration The IrDA has the serial pins summarized in table 17.1. Table 17.1 IrDA Pins Pin Name Signal Name...
Page 583: Register Configuration
17.1.4 Register Configuration The IrDA has the internal registers shown in table 17.2. These registers select IrDA or SCIF mode, specify the data format and a bit rate, and control the transmit and receive units. Table 17.2 IrDA Registers Register Name Abbreviation R/W Initial Value Address Access Size...
Page 584: Register Description
17.2 Register Description Specifications of the registers in the IrDA are the same as those in the SCIF except for the serial mode register described below. Therefore, refer to section 16, Serial Communication Interface with FIFO (SCIF), for details of these registers. 17.2.1 Serial Mode Register (SCSMR) Bit:...
Page 585 Bits 6 to 3—Ir Clock Select Bits (ICK3 to ICK0) Bit 2—Output Pulse Width Select (PSEL): PSEL selects an IrDA output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. The Ir clock select bits should be set properly to fix the output pulse width at 3/16 of the bit length for 115 kbps by setting the PSEL bit to 1.
Page 586: Operation Description
(SCSCR) is set to 1 (enabling transmission). When performing reception, clear the TE bit in SCSCR to 0. As the SH7709S's RxD1 pin is active-high in IrDA mode, a (Schmidt) inverter must be inserted when connecting an active-low IrDA module.
Page 587: Receiving
17.3.3 Receiving Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as shown in figure 17.5. Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. UART frame Data Start bit Stop bit...
Page 588: Section 18 Pin Function Controller
Section 18 Pin Function Controller 18.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the input/output direction. The pin function and input/output direction can be selected for each pin individually without regard to the operating mode of the chip. Table 18.1 lists the multiplexed pins.
Page 589 Table 18.1 List of Multiplexed Pins (cont) Port Function Other Function Port (Related Module) (Related Module) MCS0 output (BSC) PTC0 input/output (port)/PINT0 input (INTC) PTD7 input/output (port) DACK1 output (DMAC) DREQ1 input (DMAC) PTD6 input (port) PTD5 input/output (port) DACK0 output (DMAC) DREQ0 input (DMAC) PTD4 input (port) WAKEUP output (WTC)
Page 590 Table 18.1 List of Multiplexed Pins (cont) Port Function Other Function Port (Related Module) (Related Module) PTG1 input (port) AUDATA1 output (AUD) PTG0 input (port) AUDATA0 output (AUD) PTH7 input/output (port) TCLK input/output (TMU) PTH6 input (port) AUDCK input (AUD) ADTRG input (ADC) PTH5 input (port) PTH4 input (port)/IRQ4 input (INTC)
Page 591 Table 18.1 List of Multiplexed Pins (cont) Port Function Other Function Port (Related Module) (Related Module) PTL4 input (port) AN4 input (ADC) PTL3 input (port) AN3 input (ADC) PTL2 input (port) AN2 input (ADC) PTL1 input (port) AN1 input (ADC) PTL0 input (port) AN0 input (ADC) CTS2 input (UART ch 3)/IRQ5 input (INTC)
Page 592: Register Configuration
If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal mode is entered. See section 22, Hitachi User Debugging Interface (H-UDI), for more information on the H-UDI.
Page 593: Register Descriptions
18.3 Register Descriptions 18.3.1 Port A Control Register (PACR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port A control register (PACR) is a 16-bit readable/writable register that selects the pin functions.
Page 594: Port B Control Register (Pbcr)
18.3.2 Port B Control Register (PBCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port B control register (PBCR) is a 16-bit readable/writable register that selects the pin functions.
Page 595: Port C Control Register (Pccr)
18.3.3 Port C Control Register (PCCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port C control register (PCCR) is a 16-bit readable/writable register that selects the pin functions.
Page 596: Port D Control Register (Pdcr)
18.3.4 Port D Control Register (PDCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port D control register (PDCR) is a 16-bit readable/writable register that selects the pin functions.
Page 597: Port E Control Register (Pecr)
18.3.5 Port E Control Register (PECR) Bit: Initial value: 1/0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the pin functions.
Page 598: Port F Control Register (Pfcr)
18.3.6 Port F Control Register (PFCR) Bit: Initial value: 1/0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port F control register (PFCR) is a 16-bit readable/writable register that selects the pin functions.
Page 599: Port G Control Register
18.3.7 Port G Control Register (PGCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port G control register (PGCR) is a 16-bit readable/writable register that selects the pin functions.
Page 600: Port H Control Register (Phcr)
Bit (2n + 1) Bit 2n PGnMD1 PGnMD0 Pin Function Other function (n = 0–3, 5) (see table 18.1) (Initial value) (ASEMD0 = 0) Reserved Port input (Pull-up MOS: on) (Initial value) (ASEMD0 = 1) Port input (Pull-up MOS: off) (n = 0 to 3, 5) Bit (2n + 1) Bit 2n...
Page 601 Bit 15 Bit 14 PH7MD1 PH7MD0 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) (Initial value) Port input (Pull-up MOS: off) Bits 13 and 12—PH6 Mode 1 and 0 (PH6MD1, PH6MD0) Bits 11 and 10—PH5 Mode 1 and 0 (PH5MD1, PH5MD0) Bits 9 and 8—PH4 Mode 1 and 0 (PH4MD1, PH4MD0) Bits 7 and 6—PH3 Mode 1 and 0 (PH3MD1, PH3MD0) Bits 5 and 4—PH2 Mode 1 and 0 (PH2MD1, PH2MD0)
Page 602: Port J Control Register (Pjcr)
18.3.9 Port J Control Register (PJCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port J control register (PJCR) is a 16-bit readable/writable register that selects the pin functions.
Page 603: Port K Control Register (Pkcr)
18.3.10 Port K Control Register (PKCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port K control register (PKCR) is a 16-bit readable/writable register that selects the pin functions.
Page 604: Port L Control Register (Plcr)
18.3.11 Port L Control Register (PLCR) Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The port L control register (PLCR) is a 16-bit readable/writable register that selects the pin functions.
Page 605: Sc Port Control Register (Scpcr)
18.3.12 SC Port Control Register (SCPCR) Bit: SCP7 SCP7 SCP6 SCP6 SCP5 SCP5 SCP4 SCP4 SCP3 SCP3 SCP2 SCP2 SCP1 SCP1 SCP0 SCP0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The SC port control register (SCPCR) is a 16-bit readable/writable register that selects the pin functions.
Page 606 Bits 11 and 10—SCP5 Mode 1 and 0 (SCP5MD1, SCP5MD0): These bits select the pin functions and perform input pull-up MOS control. Bit 11 Bit 10 SCP5MD1 SCP5MD0 Pin Function Other function (see table 18.1) Port output Port input (Pull-up MOS: on) (Initial value) Port input (Pull-up MOS: off) Bits 9 and 8—SCP4 Mode 1 and 0 (SCP4MD1, SCP4MD0): These bits select the pin function...
Page 607 Bits 5 and 4—SCP2 Mode 1 and 0 (SCP2MD1, SCP2MD0): These bits select the pin function and perform input pull-up MOS control. Bit 5 Bit 4 SCP2MD1 SCP2MD0 Pin Function Transmit data output 1 (TxD1) Receive data input 1 (RxD1) (Initial value) General output (SCPT[2] output pin) Receive data input 1 (RxD1)
Page 608 Bits 1 and 0—SCP0 Mode 1 and 0 (SCP0MD1, SCP0MD0): These bits select the pin function and perform input pull-up MOS control. Bit 1 Bit 0 SCP0MD1 SCP0MD0 Pin Function Transmit data output 0 (TxD0) Receive data input 0 (RxD0) (Initial value) General output (SCPT[0] output pin) Receive data input 0 (RxD0)
Page 610: Section 19 I/O Ports
19.1 Overview The SH7709S has twelve 8-bit ports (ports A to L and SC). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control). Each port has a data register which stores data for the pins.
Page 611: Port A Data Register (Padr)
19.2.2 Port A Data Register (PADR) Bit: PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT Initial value: R/W: The port A data register (PADR) is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly.
Page 612: Port B
19.3 Port B Port B is an 8-bit input/output port with the pin configuration shown in figure 19.2. Each pin has an input pull-up MOS, which is controlled by the port B control register (PBCR) in the PFC. PTB7 (input/output) / D31 (input/output) PTB6 (input/output) / D30 (input/output) PTB5 (input/output) / D29 (input/output) PTB4 (input/output) / D28 (input/output)
Page 613: Port B Data Register (Pbdr)
19.3.2 Port B Data Register (PBDR) Bit: PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial value: R/W: The port B data register (PBDR) is an 8-bit readable/writable register that stores data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly.
Page 614: Port C
19.4 Port C Port C is an 8-bit input/output port with the pin configuration shown in figure 19.3. Each pin has an input pull-up MOS, which is controlled by the port C control register (PCCR) in the PFC. PTC7 (input/output) / PINT7 (input) / MSC7 (output) PTC6 (input/output) / PINT6 (input) / MSC6 (output) PTC5 (input/output) / PINT5 (input) / MSC5 (output) PTC4 (input/output) / PINT4 (input) / MSC4 (output)
Page 615: Port C Data Register (Pcdr)
19.4.2 Port C Data Register (PCDR) Bit: PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial value: R/W: The port C data register (PCDR) is an 8-bit readable/writable register that stores data for pins PTC7 to PTC0. Bits PC7DT to PC0DT correspond to pins PTC7 to PTC0. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly.
Page 616: Port D
19.5 Port D Port D comprises a 6-bit input/output port and 2-bit input port with the pin configuration shown in figure 19.4. Each pin has an input pull-up MOS, which is controlled by the port D control register (PDCR) in the PFC. PTD7 (input/output) / DACK1 (output) PTD6 (input) / DREQ1 (input) PTD5 (input/output) / DACK0 (output)
Page 617: Port D Data Register (Pddr)
19.5.2 Port D Data Register (PDDR) Bit: PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial value: R/W: Note: * Undefined The port D data register (PDDR) is a 6-bit readable/writable and 2-bit read-only register that stores data for pins PTD7 to PTD0. Bits PD7DT to PD0DT correspond to pins PTD7 to PTD0. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly.
Page 618: Port E
19.6 Port E Port E is an 8-bit input/output port with the pin configuration shown in figure 19.5. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. PTE7 (input/output) / AUDSYNC (output) PTE6 (input/output) PTE5 (input/output) / CE2B (output) PTE4 (input/output) / CE2A (output)
Page 619: Port E Data Register (Pedr)
19.6.2 Port E Data Register (PEDR) Bit: PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT Initial value: R/W: The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
Page 620: Port F
19.7 Port F Port F is an 8-bit input port with the pin configuration shown in figure 19.6. Each pin has an input pull-up MOS, which is controlled by the port F control register (PFCR) in the PFC. PTF7 (input) / PINT15 (input) / TRST (input) PTF6 (input) / PINT14 (input) / TMS (input) PTF5 (input) / PINT13 (input) / TDI (input) PTF4 (input) / PINT12 (input) / TCK (input)
Page 621: Port F Data Register (Pfdr)
19.7.2 Port F Data Register (PFDR) Bit: PF7DT PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT Initial value: R/W: Note: * Undefined The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general input port, if the port is read the corresponding pin level is read.
Page 622: Port G
19.8 Port G Port G comprises a 5-bit input/output port and 3-bit input port with the pin configuration shown in figure 19.7. Each pin has an input pull-up MOS, which is controlled by the port G control register (PGCR) in the PFC. PTG7 (input) / IOIS16 (input) PTG6 (input) / ASEMD0 (input) PTG5 (input) / ASEBRKAK (output)
Page 623: Port G Data Register
19.8.2 Port G Data Register (PGDR) Bit: PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT Initial value: R/W: Note: * Undefined The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general input port, if the port is read the corresponding pin level is read.
Page 624: Port H
19.9 Port H Port H comprises a 1-bit input/output port and 7-bit input port with the pin configuration shown in figure 19.8. Each pin has an input pull-up MOS, which is controlled by the port H control register (PHCR) in the PFC. PTH7 (input/output) / TCLK (output) PTH6 (input) / AUDCK (input) PTH5 (input) / ADTRG (input)
Page 625: Port H Data Register (Phdr)
19.9.2 Port H Data Register (PHDR) Bit: PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT Initial value: R/W: Note: * Undefined The port H data register (PHDR) is a 1-bit readable/writable and 7-bit read-only register that stores data for pins PTH7 to PTH0. Bits PH7DT to PH0DT correspond to pins PTH7 to PTH0. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly.
Page 626: Port J
19.10 Port J Port J is an 8-bit input/output port with the pin configuration shown in figure 19.9. Each pin has an input pull-up MOS, which is controlled by the port J control register (PJCR) in the PFC. PTJ7 (input/output) / STATUS1 (output) PTJ6 (input/output) / STATUS0 (output) PTJ5 (input/output) PTJ4 (input/output)
Page 627: Port J Data Register (Pjdr)
19.10.2 Port J Data Register (PJDR) Bit: PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT Initial value: R/W: The port J data register (PJDR) is an 8-bit readable/writable register that stores data for pins PTJ7 to PTJ0. Bits PJ7DT to PJ0DT correspond to pins PTJ7 to PTJ0. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly.
Page 628: Port K
19.11 Port K Port K is an 8-bit input/output port with the pin configuration shown in figure 19.10. Each pin has an input pull-up MOS, which is controlled by the port K control register (PKCR) in the PFC. PTK7 (input/output) / WE3 (output) / DQMUU (output) / ICIOWR (output) PTK6 (input/output) / WE2 (output) / DQMUL (output) / ICIORD (output) PTK5 (input/output) / CKE (output) PTK4 (input/output) / BS (output)
Page 629: Port K Data Register (Pkdr)
19.11.2 Port K Data Register (PKDR) Bit: PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT Initial value: R/W: The port K data register (PKDR) is an 8-bit readable/writable register that stores data for pins PTK7 to PTK0. Bits PK7DT to PK0DT correspond to pins PTK7 to PTK0. When the pin function is general output port, if the port is read, the value of the corresponding PKDR bit is returned directly.
Page 630: Port L
19.12 Port L Port L is an 8-bit input port with the pin configuration shown in figure 19.11. PTL7 (input) / AN7 (input) / DA0 (input) PTL6 (input) / AN6 (input) / DA1 (input) PTL5 (input) / AN5 (input) PTL4 (input) / AN4 (input) Port L PTL3 (input) / AN3 (input) PTL2 (input) / AN2 (input)
Page 631: Port L Data Register (Pldr)
19.12.2 Port L Data Register (PLDR) Bit: PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT Initial value: R/W: The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general input port, if the port is read, the corresponding pin level is read.
Page 632: Sc Port
19.13 SC Port The SC port comprises a 4-bit input/output port, 3-bit output port, and 4-bit input port with the pin configuration shown in figure 19.12. Each pin has an input pull-up MOS, which is controlled by the SC port control register (SCPCR) in the PFC. SCPT7 (input) / CTS2 (input) / IRQ5 (input) SCPT6 (input/output) / RTS2 (output) SCPT5 (input/output) / SCK2 (input/output)
Page 633: Port Sc Data Register (Scpdr)
19.13.2 Port SC Data Register (SCPDR) Bit: SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT Initial value: R/W: Note: * Undefined The port SC data register (SCPDR) is a 7-bit readable/writable and 1-bit read-only register that stores data for pins SCPT7 to SCPT0. Bits SCP7DT to SCP0DT correspond to pins SCPT7 to SCPT0.
Page 634 Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) SCPnMD1 SCPnMD0 Pin State Read Write Other function SCPDR value Value is written to SCPDR, but does (See table 18.1) not affect pin state. Output SCPDR value Write value is output from pin. Input (Pull-up Pin state Value is written to SCPDR, but does...
Page 636: Section 20 A/D Converter
Section 20 A/D Converter 20.1 Overview The SH7709S includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 20.1.1 Features A/D converter features are listed below. • 10-bit resolution • Eight input channels • High-speed conversion ...
Page 637: Block Diagram
20.1.2 Block Diagram Figure 20.1 shows a block diagram of the A/D converter. Internal Peripheral data bus data bus 10-bit φ/8 – φ/16 Analog Control circuit multi- Comparator plexer Sample-and- hold circuit interrupt signal ADTRG A/D converter Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B...
Page 638: Input Pins
20.1.3 Input Pins Table 20.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AV and AV are the power supply inputs for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage pin.
Page 639: Register Configuration
20.1.4 Register Configuration Table 20.2 summarizes the A/D converter’s registers. Table 20.2 A/D Converter Registers Name Abbreviation Initial Value Address Access size A/D data register AH ADDRAH H'00 H'04000080 16, 8 (H'A4000080)* A/D data register AL ADDRAL H'00 H'04000082 (H'A4000082)* A/D data register BH ADDRBH H'00...
Page 640: Register Descriptions
20.2 Register Descriptions 20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Upper register: H Bit: Initial value: R/W: Lower register: L Bit: — — — — — — Initial value: R/W: n = A to D The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 641: A/D Control/Status Register (Adcsr)
20.2.2 A/D Control/Status Register (ADCSR) Bit: ADIE ADST MULTI Initial value: R/W: R/(W)* Note: * Write 0 to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Page 642 Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5: ADST Description A/D conversion is stopped (Initial value) (1) Single mode: A/D conversion starts;...
Page 643: A/D Control Register (Adcr)
Channel Selection Description Single Mode Multi Mode and Scan (MULTI = 0) Mode (MULTI = 1) AN0 (Initial value) AN0, AN1 AN0 to AN2 AN0 to AN3 AN4, AN5 AN4 to AN6 AN4 to AN7 20.2.3 A/D Control Register (ADCR) Bit: TRGE1 TRGE0...
Page 644 Bits 4 and 3—Reserved (RESVD1, RESVD2): These bits are always read as 0. The write value should always be 0. Bits 2 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
Page 645: Bus Master Interface
20.3 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows.
Page 646: Operation
20.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. 20.4.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 647 Note: Vertical arrows ( ) indicate instruction execution by software. Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 648: Multi Mode (Multi = 1, Scn = 0)
20.4.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing A/D conversions on one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
Page 649 Note: * Vertical arrows ( ) indicate instruction execution by software. Figure 20.4 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected)
Page 650: Scan Mode (Multi = 1, Scn = 1)
20.4.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1)).
Page 651 Figure 20.5 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
Page 652: Input Sampling And A/D Conversion Time
20.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 20.6 shows the A/D conversion timing.
Page 653: External Trigger Input Timing
Table 20.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol A/D conversion start — — delay Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states (t 20.4.5 External Trigger Input Timing A/D conversion can be externally triggered.
Page 654: Interrupts
20.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 20.6 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data.
Page 655: Usage Notes
(2) Full-scale error Digital output Digital output Ideal A/D Ideal A/D conversion conversion characteristic characteristic (4) Nonlinearity error (3) Quantization Actual A/D error convertion characteristic 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input Analog input (1) Offset error voltage voltage FS: Full-scale voltage...
Page 656: Access Size And Read Data
The case is shown here in which H'3FF is obtained when AV is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. SH7709S 100 Ω AN0 to AN7 0.1 µF Note: 10 µF...
Page 657 Table 20.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ Table 20.6 Relationship between Access Size and Read Data Bus Width 32 Bits (D31–D0) 16 Bits (D15–D0) 8 Bits (D7–D0) Endian Access Size Command Little Little...
Page 658: Section 21 D/A Converter
Section 21 D/A Converter 21.1 Overview The SH7709S includes a D/A converter with two channels. 21.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 659: I/O Pins
21.1.3 I/O Pins Table 21.1 summarizes the D/A converter’s input and output pins. Table 21.1 D/A Converter Pins Pin Name Abbreviation Function Analog power supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0...
Page 660: Register Descriptions
21.2 Register Descriptions 21.2.1 D/A Data Registers 0 and 1 (DADR0/1) Bit: Initial value: R/W: The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 661 Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When the chip enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion.
Page 662: Operation
21.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 664: Section 22 Hitachi User Debugging Interface (H-Udi)
Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary- Scan Architecture) specifications. The H-UDI in the SH7709S supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator.
Page 665: Block Diagram
mode, boundary scan and emulator functions can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. ASEBRKAK: Dedicated emulator pin 22.2.2 Block Diagram Figure 22.1 shows a block diagram of the H-UDI. SDBPR SDIR Local...
Page 666: Bypass Register Sdbpr
Table 22.1 shows the H-UDI register configuration. Table 22.1 H-UDI Registers CPU Side H-UDI Side Initial Name Abbreviation Size Address Size Value* Bypass register SDBPR — — — Undefined Instruction register SDIR H'04000200 H'FFFF Boundary register SDBSR — — — —...
Page 667: Boundary Scan Register (Sdbsr)
Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register, located on the PAD, for controlling the input/output pins of the SH7709S. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 22.3 shows the correspondence between the pins of this...
Page 668 Table 22.3 Pins of this LSI and Boundary Scan Register Bits Pin Name Pin Name from TDI D31/PTB7 D30/PTB6 D29/PTB5 D28/PTB4 D27/PTB3 IRQ0/IRL0/PTH0 D26/PTB2 IRQ1/IRL1/PTH1 D25/PTB1 IRQ2/IRL2/PTH2 D24/PTB0 IRQ3/IRL3/PTH3 D23/PTA7 IRQ4/PTH4 D22/PTA6 D31/PTB7 D21/PTA5 D30/PTB6 D20/PTA4 D29/PTB5 D19/PTA3 D28/PTB4 D18/PTA2 D27/PTB3 D17/PTA1 D26/PTB2...
Page 669 Table 22.3 Pins of this LSI and Boundary Scan Register Bits (cont) Pin Name Pin Name Control Control Control Control Control Control Control Control Control Control Control D31/PTB7 Control Control D30/PTB6 Control Control BS/PTK4 D29/PTB5 Control WE2/DQMUL/ICIORD/ D28/PTB4 Control PTK6 WE3/DQMUU/ICIORD/ D27/PTB3 Control...
Page 670 Table 22.3 Pins of this LSI and Boundary Scan Register Bits (cont) Pin Name Pin Name CS4/PTK2 CS5/CE1A/PTK3 CS6/CE1B CE2A/PTE4 CE2B/PTE5 Control Control Control Control Control Control Control Control Control Control Control Control Control Control BS/PTK4 Control Control WE0/DQMLL Control WE1/DQMLU/WE Control WE2/DQMUL/ICIORD/...
Page 671 Table 22.3 Pins of this LSI and Boundary Scan Register Bits (cont) Pin Name Pin Name BREQ Control WAIT BS/PTK4 Control Control AUDCK/PTH6 WE0/DQMLL IOIS16/PTG7 Control WE1/DQMLU/WE ASEBRKAK/PTG5 Control WE2/DQMUL/ICIORD/ Control CKIO2/PTG4 PTK6 WE3/DQMUU/ICIOWR/ Control AUDATA3/PTG3 PTK7 RD/WR Control AUDATA2/PTG2 AUDSYNC/PTE7 Control AUDATA1/PTG1...
Page 672 Table 22.3 Pins of this LSI and Boundary Scan Register Bits (cont) Pin Name Pin Name ASEBRKAK/PTG5 RxD2/SCPT4 WAKEUP/PTD3 AUDATA3/PTG3 RESETOUT/PTD2 AUDATA2/PTG2 AUDATA1/PTG1 DRAK0/PTD1 AUDATA0/PTG0 DRAK1/PTD0 DREQ0/PTD4 CKE/PTK5 Control RAS3L/PTJ0 DREQ1/PTD6 Control PTJ1 Control RxD1/SCPT2 CASL/PTJ2 CTS2/IRQ5/SCPT7 Control CASU/PTJ3 MCS7/PTC7/PINT7 Control MCS6/PTC6/PINT6 PTJ4...
Page 673 Table 22.3 Pins of this LSI and Boundary Scan Register Bits (cont) Pin Name Pin Name MCS6/PTC6/PINT6 SCK1/SCPT3 Control MCS5/PTC5/PINT5 TxD2/SCPT4 Control MCS4/PTC4/PINT4 SCK2/SCPT5 Control WAKEUP/PTD3 RTS2/SCPT6 Control RESETOUT/PTD2 MCS7/PTC7/PINT7 Control MCS3/PTC3/PINT3 MCS6/PTC6/PINT6 Control MCS2/PTC2/PINT2 MCS5/PTC5/PINT5 Control MCS1/PTC1/PINT1 MCS4/PTC4/PINT4 Control MCS0/PTC0/PINT0 WAKEUP/PTD3 Control...
Page 674: H-Udi Operation
22.4 H-UDI Operation 22.4.1 TAP Controller Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform with the JTAG standard. Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 22.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK.
Page 675: Reset Configuration
22.4.2 Reset Configuration Table 22.4 Reset Configuration ASDMD0* RESETP TRST Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold* Normal reset H-UDI reset only Normal operation Notes: *1 Selects main chip mode or ASE mode ASEMD0 = H, normal mode ASEMD0 = L, ASE mode Set ASEMD0 = H when using on the user system alone, without an emulator and the...
Page 676: H-Udi Interrupt
H-UDI reset assert H-UDI reset negate SDIR Chip internal reset CPU state Branch to H'A0000000 Figure 22.3 H-UDI Reset 22.4.4 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and with return by the RTE instruction.
Page 677 chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path.
Page 678: Points For Attention
22.5.2 Points for Attention 1. Boundary scan mode covers clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO). 2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM, CA). 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4.
Page 680: Section 23 Electrical Characteristics
Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 shows the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage (I/O) VccQ –0.3 to 4.2 Power supply voltage (internal) Vcc –0.3 to 2.5 Vcc –...
Page 681 (Max. 100 µs) 3.3 V 3.3 V power 1.7 V/1.8 V/1.9 V/2.0 V 1.7 V/1.8 V/1.9 V/2.0 V power RESETP Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence •...
Page 682: Dc Characteristics
23.2 DC Characteristics Tables 23.2 and 23.3 list DC characteristics. Table 23.2 DC Characteristics (V Q = 3.3 ± 0.3 V, V = 1.55 to 2.15 V, AV = 3.3 ± 0.3 V, Ta = –20 to 75°C) Item Symbol Unit Measurement Conditions Power supply voltage...
Page 683 Table 23.2 DC Characteristics (V Q = 3.3 ± 0.3 V, V = 1.55 to 2.15 V, AV = 3.3 ± 0.3 V, Ta = –20 to 75°C)(cont) Item Symbol Unit Measurement Conditions RESETP, Input high VccQ — VccQ + ×...
Page 684 Table 23.2 DC Characteristics (V Q = 3.3 ± 0.3 V, V = 1.55 to 2.15 V, AV = 3.3 ± 0.3 V, Ta = –20 to 75°C)(cont) Item Symbol Min Unit Measurement Conditions RESETP, Input low –0.3 — VccQ ×...
Page 685 Table 23.2 DC Characteristics (V Q = 3.3 ± 0.3 V, V = 1.55 to 2.15 V, AV = 3.3 ± 0.3 V, Ta = –20 to 75°C)(cont) Item Symbol Min Unit Measurement Conditions Analog AVcc power- supply voltage Analog During A/D AIcc —...
Page 686: Ac Characteristics
23.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 23.4 Maximum Operating Frequencies (VccQ = 3.3 ± 0.3 V, VccQ = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) Item Symbol...
Page 687: Clock Timing
23.3.1 Clock Timing Table 23.5 Clock Timing (1) (VccQ = 3.3 ± 0.3 V, VccQ = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 25 MHz) Item Symbol Unit Figure EXTAL clock input frequency...
Page 688 Table 23.5 Clock Timing (1) (cont) (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 25 MHz) Item Symbol Unit Figure PLL synchronization settling time 1 —...
Page 689 Table 23.5 Clock Timing (2) (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 33 MHz) Item Symbol Unit Figure EXTAL clock input frequency 6.25 23.1 EXTAL clock input cycle time...
Page 690 Table 23.5 Clock Timing (2) (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 33 MHz)(cont) Item Symbol Unit Figure PLL synchronization settling time 1 —...
Page 691 Table 23.5 Clock Timing (3) (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 66 MHz) Item Symbol Unit Figure EXTAL clock input frequency 6.25 23.1 EXTAL clock input cycle time...
Page 692 Table 23.5 Clock Timing (4) (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 66 MHz) Item Symbol Unit Figure Standby return oscillation settling time 1 t —...
Page 693 EXcyc EXTAL* (input) 1/2 V 1/2 V Note: * The clock input from the EXTAL pin. Figure 23.1 EXTAL Clock Input Timing CKIcyc CKIH CKIL CKIO (input) 1/2 V 1/2 V CKIR CKIF Figure 23.2 CKIO Clock Input Timing...
Page 694 CKOH CKOL CKIO (output) 1/2V 1/2V CKOF CKOR CK2D CK2D CKIO2 (output) CK2OF CK2OR Figure 23.3 CKIO Clock Output Timing Stable oscillation CKIO, internal clock RESP/MW RESP/MS OSC1 RESETP RESETM Note: Oscillation settling time when built-in oscillator is used Figure 23.4 Power-on Oscillation Settling Time...
Page 695 Standby Stable oscillation CKIO, internal clock RESP/MW OSC2 RESETP RESETM Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode Figure 23.5 Oscillation Settling Time at Standby Return (Return by Reset) Standby Stable oscillation CKIO, internal clock OSC3 WAKEUP...
Page 696 Standby Stable oscillation CKIO, internal clock OSC4 IRL3 to IRL0 IRQ4 to IRQ0 PINT0/1 WAKEUP Note: Oscillation settling time when built-in oscillator is used in the oscillation off mode (only when RTC is used) Figure 23.7 Oscillation Settling Time at Standby Return (Return by IRQ4 to IRQ0, PINT0/1, IRL3 to IRL0) Reset or NMI interrupt request Stable input clock...
Page 697 IRQ4 – IRQ0/IRL3 – IRL0 interrupt request Stable input clock Stable input clock EXTAL input or CKIO input PLL synchronization PLL synchronization IRLSTB PLL1 PLL output, CKIO output Internal clock STATUS 0 Normal Standby Normal STATUS 1 during the continued oscillation mode or Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin Figure 23.9 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt...
Page 698: Control Signal Timing
23.3.2 Control Signal Timing Table 23.6 Control Signal Timing (Vcc = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) to 66* Item Symbol Unit Figure RESETP pulse width 20 * —...
Page 699 CKIO RESPS/MS RESPS/MS RESPW/MW RESETP RESETM Figure 23.11 Reset Input Timing CKIO RESPH/MH RESPS/MS RESETP RESETM NMIH NMIS IRQH IRQS IRQ5 to IRQ0 Figure 23.12 Interrupt Signal Input Timing CKIO IRQOD IRQOD IRQOUT Figure 23.13 IRQOUT Timing...
Page 700 CKIO BREQH BREQS BREQH BREQS BREQ BACKD BACKD BACK BON2 BOFF2 RD, RD/WR , RAS, CAS , CSn, WEn, BS, BON1 MCSn BOFF1 A25 to A0, D31 to D0 Figure 23.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO STATUS 0 STATUS 1...
Page 701: Ac Bus Timing
23.3.3 AC Bus Timing Table 23.7 Bus Timing (Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) to 66* Item Symbol Unit Figure Address delay time 23.16–23.36, 23.39–23.46 Address setup time...
Page 702 Table 23.7 Bus Timing (cont) (Clock Modes 0/ 1/ 2/ 7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) to 66* Item Symbol Unit Figure Write data hold time 1 —...
Page 703: Basic Timing
23.3.4 Basic Timing CKIO A25 to A0 CSD1 CSD2 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD1 DAKD1 DACKn Figure 23.16 Basic Bus Cycle (No Wait)
Page 704 CKIO A25 to A0 CSD2 CSD1 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD1 DAKD1 DACKn WAIT Figure 23.17 Basic Bus Cycle (One Wait)
Page 705 CKIO A25 to A0 CSD1 CSD2 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD2 DAKD1 DACKn WAIT Figure 23.18 Basic Bus Cycle (External Wait, WAITSEL = 1)
Page 706: Burst Rom Timing
23.3.5 Burst ROM Timing CKIO A25 to A4 A3 to A0 CSD1 CSD2 RDH1 RD/WR RDH1 RDH1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. Figure 23.19 Burst ROM Bus Cycle (No Wait)
Page 707 CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WE RDH1 RDH1 RDH1 RDS1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.20 Burst ROM Bus Cycle (Two Waits)
Page 708 CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WR RSD1 RSD1 RDH1 RDH1 RDS1 D31 to D0 DAKD2 DAKD1 DACKn WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1)
Page 709: Synchronous Dram Timing
23.3.6 Synchronous DRAM Timing (Tpc) CKIO Row address A25 to A16 Read A A12 or A10 Row address command A15 to A0 Row address Column address tCSD3 tCSD3 tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD...
Page 710 (Tpc) (Tpc) CKIO A25 to A16 Row address Read A A12 or A10 Row address command Row address Column address A15 to A0 tCSD3 tCSD3 tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD (High)
Page 711 Tc2/Td1 Tc3/Td2 Tc4/Td3 (Tpc) (Tpc) CKIO A25 to A16 Row address Read A Read command A12 or A10 address command Column address (1-4) A15 to A0 address tCSD3 tCSD3 tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD...
Page 712 Tc3 Tc4/Td1 Td2 (Tpc) CKIO A25 to A16 Row address A12 or A10 Read command address A15 to A0 Column address (1-4) address tCSD3 tCSD3 tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 (read) tBSD tBSD...
Page 713 (Trwl) (Tpc) CKIO A25 to A16 Row address A12 or A10 Write A Row address command Row address Column address A15 to A0 tCSD3 tCSD3 tRWD tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tWDD2 tWDH2 D31 to D0 tBSD tBSD (High)
Page 714 (Trwl) (Trwl) (Tpc) (Tpc) CKIO A25 to A16 Row address A12 or A10 Write A address command Column A15 to A0 address address tCSD1 tCSD1 tRWD tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tWDD2 tWDH2 D31 to D0 tBSD tBSD (High)
Page 715 (Trwl) (Tpc) (Tpc) CKIO A25 to A16 Row address A12 or A10 Write A Write command address command A15 to A0 Column address (1-4) address tCSD3 tCSD3 tRWD tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tWDD2 tWDD2 tWDH2 D31 to D0 tBSD...
Page 716 (Trwl) (Tpc) CKIO A25 to A16 Row address Write A A12 or A10 Write command address command Column address (1-4) A15 to A0 address tCSD3 tCSD3 tRWD tRWD tRWD RD/WR tRASD2 tRASD2 tCASD2 tCASD2 tDQMD tDQMD DQMxx tWDD2 tWDD2 tWDH2 D31 to D0 tBSD tBSD...
Page 717 Tnop Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25 to A16 Row address Read command A12 or A10 Column address A15 to A0 CSD3 CSD3 RD/WR RASD2 CASD2 CASD2 DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1 DACKn Figure 23.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1)
Page 718 Tnop Tc3/Td1 Tc4/Td2 CKIO A25 to A16 Row address Read command A12 or A10 A15 to A0 Column address CSD3 CSD3 RD/WR RASD2 CASD2 CASD2 DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1 DACKn Figure 23.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2)
Page 719 Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Row address A25 to A16 Read command A12 or A10 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD2 RASD2 CASD2 CASD2 DQMD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1 DACKn...
Page 720 Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Row address A25 to A16 Read command A12 or A10 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD2 RASD2 RASD2 RASD2 CASD2 CASD2 DQMD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 (High) t DAKD1 t DAKD1 DACKn Figure 23.33 Synchronous DRAM Burst Read Bus Cycle...
Page 721 CKIO Row address A25 to A16 Write command A12 or A10 Column address A15 to A0 CSD3 CSD3 RD/WR RASD2 RASD2 CASD2 CASD2 DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (High) t DAKD1 t DAKD1 DACKn Figure 23.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address)
Page 722 CKIO Row address A25 to A16 Write command A12 or A10 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD2 RASD2 CASD2 CASD2 DQMD DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (High) t DAKD1 t DAKD1 DACKn Figure 23.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0)
Page 723 CKIO Row address A25 to A16 Write command A12 or A10 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD2 RASD2 RASD2 RASD2 CASD2 CASD2 DQMD DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (High) t DAKD1 t DAKD1 DACKn Figure 23.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1)
Page 724 TRrw TRrw (Tpc) (Tpc) CKIO (High) CSD3 CSD3 CSD3 CSD3 RASD2 RASD2 RASD2 RASD2 RAS3x CASD2 CASD2 CASxx RD/WR Figure 23.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1)
Page 725 TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO CKED CKED CSD3 CSD3 CSD3 CSD3 RASD2 RASD2 RASD2 RASD2 CASD2 CASD2 RD/WR Figure 23.38 Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1)
Page 726 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO A13 or A11 A12 or A10 A11 to A2 or A9 to A2 tCSD3 tCSD3 tRWD tRWD tRWD RD/WR tRASD2 tRASD2 tRASD2 tRASD2 tCASD2 tCASD2 CASxx D31 to D0 (High) t DAKD1 t DAKD1 DACKn Figure 23.39 Synchronous DRAM Mode Register Write Cycle...
Page 727: Pcmcia Timing
23.3.7 PCMCIA Timing pcm1 pcm2 CKIO A25 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDS1 D15 to D0 (read) (write) WDH4 WDD1 WDH1 D15 to D0 (write) DAKD1 DAKD1 DACKn Figure 23.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait)
Page 728 pcm0 pcm0w pcm1 pcm1w pcm1w pcm2 pcm2w CKIO A25 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDS1 D15 to D0 (read) (write) WDH4 WDD1 WDH1 D15 to D0 (write) DAKD1 DAKD1 DACKn WAIT Figure 23.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1)
Page 729 pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 23.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)
Page 730 pcm0 pcm1 pcm1w pcm1w pcm1w pcm2 pcm1 pcm1w pcm2 pcm2w CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn WAIT Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 23.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1)
Page 731 pci1 pci2 CKIO A25 to A0 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICIORD (read) RDH1 RDS1 D15 to D0 (read) ICWSD ICWSD ICIOWR (write) WDH4 WDH1 WDD1 D15 to D0 (write) DAKD1 DAKD1 DACKn Figure 23.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)
Page 732 pci0 pci0w pci1 pci1w pci1w pci2 pci2w CKIO A25 to A0 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICIORD (read) RDH1 RDS1 D15 to D0 (read) ICWSD ICWSD ICIOWR (write) WDH4 WDH1 WDD1 D15 to D0 (write) DAKD1 DAKD1 DACKn WAIT IO16S IO16H IOIS16...
Page 733 pci0 pci1 pci1w pci2 pci1 pci1w pci2 pci2w CKIO A25 to A4 CSD1 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICRSD ICRSD ICIORD (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) ICWSD ICWSD ICWSD ICWSD ICIOWR (write) WDH4 WDH4 WDD1 WDD1 WDH1 D15 to D0...
Page 734: Peripheral Module Signal Timing
23.3.8 Peripheral Module Signal Timing Table 23.8 Peripheral Module Signal Timing (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) to 66 Module Item Symbol Unit Figure TMU, Timer input setup time...
Page 735 CKIO TCLKS TCLK (input) Figure 23.47 TCLK Input Timing TCKS CKIO TCKS TCLK (input) TCKWL TCKWH Figure 23.48 TCLK Clock Input Timing Stable oscillation RTC crystal oscillator CCmin ROSC Figure 23.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on SCKW SCKR SCKF (input)
Page 736 SCYC (data trans- missiion) (data reception) RTSD CTSS CTSH Figure 23.51 SCI I/O Timing in Clock Synchronous Mode CKIO PORTS1 PORTH1 PORT 7 to 0 (read) (B:P clock ratio = 1:1) PORTS2 PORTH2 PORT 7 to 0 (read) (B:P clock ratio = 2:1) PORTS3 PORTH3 PORT 7 to 0...
Page 737: H-Udi-Related Pin Timing
CKIO DRAKD DRAKD DRAK0/1 Figure 23.54 DRAK Output Timing 23.3.9 H-UDI-Related Pin Timing Table 23.9 H-UDI-Related Pin Timing Q = 3.3 ± 0.3V, V = 3.3 ± 0.3V, Ta = –20 to 75°C) = 1.55 to 2.15 V, AV Item Symbol Unit Figure...
Page 738 RESETP TRSTS TRSTH TRST Figure 23.56 TRST Input Timing (Reset Hold) TCKCYC TDIS TDIH TMSS TMSH TDOD Figure 23.57 H-UDI Data Transfer Timing RESETP ASEMD0S ASEMD0H ASEMD0 Figure 23.58 ASEMD0 Input Timing...
Page 739: 23.3.10 Ac Characteristics Measurement Conditions
23.3.10 AC Characteristics Measurement Conditions • I/O signal reference level: V Q/2 (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V) • Input pulse level: Vss to 3.0 V (where RESETP, RESETM, ASEND0, IRLS3 to IRLS0, IRL3 to IRL0, ADTRG, PINT15 to PINT0, TRST, RxD1, CA, NMI, IRQ5–IRQ0, CKIO, and MD5–MD0 are within Vss to Vcc) •...
Page 740: 23.3.11 Delay Time Variation Due To Load Capacitance
23.3.11 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 or 50 pF) is connected to this LSI's pins is shown below. The graph shown in figure 23.60 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device.
Page 741: A/D Converter Characteristics
23.4 A/D Converter Characteristics Table 23.10 lists the A/D converter characteristics. Table 23.10 A/D Converter Characteristics (VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C) Item Unit Resolution bits...
Page 742: Appendix A Pin Functions
Appendix A Pin Functions Pin States Table A.1 shows pin states during resets, power-down states, and the bus-released state. Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released Clock EXTAL XTAL...
Page 743 Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State (cont) Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released Address bus A[25:0] Data bus D[15:0] D[23:16]/PTA[7:0] IOP* D[31:24]/PTB[7:0] IOP* CS0/MCS0 Bus control CS[2:4]/PTK[0:2] CS5/CE1A/PTK[3] CS6/CE1B BS/PTK[4] RAS3L/PTJ[0] ZOK* ZOP* RAS3U/PTE[2]...
Page 744 Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State (cont) Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released DREQ0/PTD[4] DMAC DACK0/PTD[5] DRAK0/PTD[1] DREQ1/PTD[6] DACK1/PTD[7] DRAK1/PTD[0] Timer TCLK/PTH[7] IOP* IOP* IOP* SCI/ Smart card RxD0/SCPT[0] without FIFO TxD0/SCPT[0] SCK0/SCPT[1] IOP*...
Page 745 Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State (cont) Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released ASEMD0/PTG[6] Port PTJ[1] ZOK* ZOP* PTE[1]* ZOK* ZOP* PTE[6] ZOK* ZOP* PTE[3] ZOK* ZOP* PTJ[4] ZOK* ZOP* PTJ[5] ZOK* ZOP* Analog...
Page 746: Pin Specifications
Pin Specifications Table A.2 shows the pin specifications. Table A.2 Pin Specifications Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) Operating mode pin (endian mode) MD4, MD3 196, 195 D6, A7 Operating mode pin (area 0 bus width) MD2 to MD0 2, 1, 144 C2, D2,G19 Operating mode pin (clock mode)
Page 747 Table A.2 Pin Specifications (cont) Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) A25 to A0 86, 84, 82, 80, V12, T12, Address bus 78 to 72, 70, V11, W10, 68 to 60, 58, V10, U9, T9, 56 to 53 V9, W9, T8, V8, W8, U7, V7, W7, T6,...
Page 748 Table A.2 Pin Specifications (cont) Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) CS3/PTK[1] Chip select 3 / I/O port CS2/PTK[0] Chip select 2 / I/O port CS0/MCS0 Chip select 0 / Mask ROM chip select 0 BS/PTK[4] Bus cycle start / I/O port PTJ[5] I/O port PTJ[4]...
Page 749 Table A.2 Pin Specifications (cont) Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) ASMD0/PTG[6] ASE mode / input port ASEBRKAK/ ASE break accept / input port PTG[5] CKIO2/PTG[4] System clock output / input port AUDATA[3]/ AUD data / input port PTG[3] AUDATA[2]/ AUD data / input port...
Page 750 Table A.2 Pin Specifications (cont) Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) CTS2/IRQ5/ Serial port 2 transfer enable / SCPT[7] external interrupt request / input port TCLK/PTH[7] Clock I/O (for TMU/RTC) / I/O port EXTAL External clock / crystal oscillator pin XTAL Crystal oscillator pin CAP1...
Page 751: Treatment Of Unused Pins
Table A.2 Pin Specifications (cont) Pin No. Pin No. Function (FP-208C, (BP-240A) FP-208E) –RTC Power RTC-oscillator power supply (0 V) supply –PLL1 Power PLL power supply (0 V) –PLL2 supply 198, 208 B6, B4 Power Analog power supply (0 V) supply Note: Except in hardware standby mode, power must be supplied constantly to all power supply pins.
Page 752: Pin States In Access To Each Address Space
Pin States in Access to Each Address Space Table A.3 Pin States (Ordinary Memory/Little Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 753 Table A.3 Pin States (Ordinary Memory/Little Endian) (cont) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 754 Table A.4 Pin States (Ordinary Memory/Big Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled High High High High RD/WR High High...
Page 755 Table A.4 Pin States (Ordinary Memory/Big Endian) (cont) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 756 Table A.5 Pin States (Burst ROM/Little Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled — — — — RD/WR High High...
Page 757 Table A.5 Pin States (Burst ROM/Little Endian) (cont) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 758 Table A.6 Pin States (Burst ROM/Big Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled — — — — RD/WR High High...
Page 759 Table A.6 Pin States (Burst ROM/Big Endian) (cont) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 760 Table A.7 Pin States (Synchronous DRAM/Little Endian) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 761 Table A.8 Pin States (Synchronous DRAM/Big Endian) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access (Address (Address (Address (Address (Address (Address Longword 4n + 1) 4n + 2) 4n + 3) 4n + 2) Access CS6 to CS2, CS0 Enabled...
Page 762 Table A.9 Pin States (PCMCIA/Little Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled High Enabled High High High...
Page 763 Table A.9 Pin States (PCMCIA/Little Endian) (cont) PCMCIA Memory Interface PCMCIA/IO Interface (Area 6) (Area 6) 8-Bit 8-Bit Width 16-Bit Bus Width Width 16-Bit Bus Width Byte/ Byte Byte Byte/ Byte Byte Word/ Access Access Word/ Word/ Access Access Word/ Long- (Ad- (Ad-...
Page 764 Table A.10 Pin States (PCMCIA/Big Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/Long- Byte Access Byte Access Word/Longword word Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled High Enabled High High High...
Page 765 Table A.10 Pin States (PCMCIA/Big Endian) (cont) PCMCIA Memory Interface PCMCIA/IO Interface (Area 6) (Area 6) 8-Bit 8-Bit Width 16-Bit Bus Width Width 16-Bit Bus Width Byte/ Byte Byte Byte/ Byte Byte Word/ Access Access Word/ Word/ Access Access Word/ Long- (Ad- (Ad-...
Page 766: Appendix B Memory-Mapped Control Registers
Appendix B Memory-Mapped Control Registers Register Address Map Table B.1 Memory-Mapped Control Registers Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* PTEH FFFFFFF0 PTEL FFFFFFF4 FFFFFFF8 FFFFFFFC MMUCR FFFFFFE0 BASRA FFFFFFE4 BASRB FFFFFFE8 FFFFFFEC CCR2 40000B0 FFFFFFD0 EXPEVT FFFFFFD4 INTEVT FFFFFFD8...
Page 767 Table B.1 Memory-Mapped Control Registers (cont) Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* WCR1 FFFFFF64 WCR2 FFFFFF66 BETR FFFFFF9C BRSR FFFFFFAC BRDR FFFFFFBC FFFFFF68 FFFFFF6C RTCSR FFFFFF6E RTCNT FFFFFF70 RTCOR FFFFFF72 RFCR FFFFFF74 SDMR FFFFD000– — FFFFEFFE MCSCR0 FFFFFF50 MCSCR1...
Page 768 Table B.1 Memory-Mapped Control Registers (cont) Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* RWKAR FFFFFED6 RDAYAR FFFFFED8 RMONAR FFFFFEDA RCR1 FFFFFEDC RCR2 FFFFFEDE ICR0 INTC FFFFFEE0 IPRA INTC FFFFFEE2 IPRB INTC FFFFFEE4 TOCR FFFFFE90 TSTR FFFFFE92 TCOR0 FFFFFE94 TCNT0 FFFFFE98...
Page 769 Table B.1 Memory-Mapped Control Registers (cont) Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* PINTER INTC 4000014 IPRC INTC 4000016 IPRD INTC 4000018 IPRE INTC 400001A SAR0 DMAC 4000020 16,32 DAR0 DMAC 4000024 16,32 DMATCR0 DMAC 4000028 16,32 CHCR0 DMAC 400002C...
Page 770 Table B.1 Memory-Mapped Control Registers (cont) Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* ADDRDL 400008E 8,16* ADCSR 4000090 8,16,32* ADCR 4000092 8,16 DADR0 40000A0 8,16,32* DADR1 40000A2 8,16* DACR 40000A4 8,16,32 PACR PORT 4000100 PBCR PORT 4000102 PCCR PORT 4000104...
Page 771 Table B.1 Memory-Mapped Control Registers (cont) Control Register Module* Bus* Address* Size (Bits) Access Size (Bits)* SCSCR1 IrDA 4000144 SCFTDR1 IrDA 4000146 SCSSR1 IrDA 4000148 SCFRDR1 IrDA 400014A SCFCR1 IrDA 400014C SCFDR1 IrDA 400014E SCSMR2 SCIF 4000150 SCBRR2 SCIF 4000152 SCSCR2 SCIF 4000154...
Page 772: Register Bits
Register Bits Table B.2 Register Bits Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SDMR — — — — SCSMR STOP CKS1 CKS0 SCBRR SCSCR MPIE TEIE CKE1 CKE0 SCTDR SCSSR TDRE RDRF...
Page 773 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR1 — — — — — — — — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR2 TCNT2 TCR2 —...
Page 774 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RCR1 — — — — RCR2 PES2 PES1 PES0 RTCEN ADJ RESET START RTC ICR0 — — —...
Page 775 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RFCR — — — — — — — — FRQCR STC2 IFC2 PFC2 — — — SLPFR CKOEN CPG PLLEN PSTBY...
Page 776 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BARA BAMRA BBRA — — — — — — — — CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 BETR...
Page 777 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MMUCR — — — — — — — — — — — — — — — — —...
Page 778 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTEVT2 INTC IRR0 INTC PINT0R PINT1R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R IRR1 INTC TXI1R BRI1R RXI1R ERI1R DEI3R DEI2R...
Page 779 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMATCR0 — — — — — — — — DMAC CHCR0 — — — — — — —...
Page 780 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMATCR2 — — — — — — — — DMAC CHCR2 — — — — — — —...
Page 781 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CMCOR ADDRAH ADDRAL — — — — — — ADDRBH ADDRBL — — — — — — ADDRCH ADDRCL —...
Page 782 Table B.2 Register Bits (cont) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PFCR PF7M PF7M PF6M PF6M PF5M PF5M PF4M PF4M PORT PF3M PF3M PF2M PF2M PF1M PF1M PF0M PF0M PGCR PG7M...
Page 783 Table B.2 Register Bits (cont) Register BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Module PJDR PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT PORT PKDR PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT PK1DT PK0DT PORT PLDR PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT PL1DT PL0DT PORT SCPDR SCP7DT SCP6DT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT PORT SDIR...
Page 784: Appendix C Product Lineup
Appendix C Product Lineup Table C.1 SH7709S Models Power Supply Voltage Operating Abbr. Internal Frequency Model Marking Package 3.3 ±0.3 V 1.9 ±0.15 V SH7709S 167 MHz HD6417709SF167 208-pin plastic LQFP (FP-208C) 1.8 ±0.15 V 133 MHz HD6417709SF133 208-pin plastic LQFP...
Page 785: Appendix D Package Dimensions
Appendix D Package Dimensions Figures D.1 to D.3 show the SH7709S package dimensions. Unit: mm 30.0 ± 0.2 *0.22 ± 0.05 0.08 M 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.08 Hitachi Code FP-208C JEDEC — EIAJ...
Page 786 Unit: mm 30.6 ± 0.2 *0.22 ± 0.05 0.10 M 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code FP-208E JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 5.3 g Base material dimension...
Page 787 Preliminary 13.00 0.20 C A 0.65 4× 0.15 0.65 240 × φ0.40 ± 0.05 φ0.08 0.10 Figure D.3 Package Dimensions (BP-240AV)
Page 788 SH7709S Hardware Manual Publication Date: 1st Edition, September 2001 Published by: Customer Service Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.