Basic Timing - Hitachi SH7032 Hardware Manual

For example, when MXC1 and MXC0 are set to 00 and an 8-bit shift is selected, the A23–A8
address bit values are output to pins A15–A0 the row address. The values for A21–A16 are
undefined. The values of bits address A21–A0 are output to pins A21–A0 as the column address.
Figure 8.16 depicts address multiplexing with an 8-bit shift.
RAS = Low
Internal address
Address pin
CAS = Low
Internal address
Address pin
Figure 8.16 Address Multiplexing States (8-Bit Shift)
8.5.2

Basic Timing

There are two types of DRAM accesses: short pitch and long pitch. Short pitch or long pitch can
be selected for the respective bus cycles using the RW1 and WW1 bits in WCR1 and the DRW1
and DWW1 bits in WCR2. When the corresponding bits are cleared to 0, DRAM access is short
pitch and column address output occurs in 1 state. When these bits are 1, DRAM access is long
pitch and column address output occurs in 2 states. Figure 8.17 shows short pitch timing; figure
8.18 shows long pitch timing.
The high-level duty of the CAS signal can also be selected between 50% and 35% of the TC state
when access is short pitch. By setting the CDTY bit to 1, the high level duty becomes 35% and the
DRAM access time can be lengthened. Only set to 1 when the operating frequency is a minimum
of 10 MHz.
144
A23
A21 A16 A15
Undefined output
A23 A22 A21
A21
A8 A7 A0
A0
A0
A0