Refresh Timer Control/Status Register (Rtcsr) Bsc - Hitachi SH7032 Hardware Manual

A.2.47 Refresh Timer Control/Status Register (RTCSR)
• Start Address: H'5FFFFAE
• Bus Width: 8/16/32 (read), 16 (write)
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.48 RSTCR Bit Functions
Bit Bit Name
7 Compare match flag (CMF) 0
6 Compare match interrupt
enable (CMIE)
5–3 Clock select 2–0 (CKS2–
CKS0)
15 14
— —
0 0
— —
7 6
CMF CMIE CKS2
0 0
R/W R/W R/W
Value
1
0
1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
13 12 11
— — —
0 0 0
— — —
5 4 3
CKS1 CKS0
0 0 0
R/W R/W
Description
RTCNT and RTCOR values do not match(Initial value)
Clear Condition: CMF read, then 0 written in CMF
RTCNT and RTCOR values match
Compare match interrupt (CMI) disabled (Initial value)
Compare match interrupt (CMI) enabled
0 Clock input disabled
φ/2
1
φ/8
0
φ/32
1
φ/128
0
φ/512
1
φ/2048
0
φ/4096
1
BSC
10 9 8
— — —
0 0 0
— — —
2 1 0
— — —
0 0 0
— — —
(Initial value)
615