Hitachi SH7032 Hardware Manual page 397

Bit 3: PER Description
0 Receiving is in progress or has ended normally
Clearing the RE bit to 0 in the serial control register does not affect the PER bit,
which retains its previous value.
PER is cleared to 0 when:
•
•
1 A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into RDR but does not set RDRF. Serial receiving cannot continue
while PER is set to 1. In synchronous mode, serial transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR).
• Bit 2 (Transmit End (TEND)): TEND indicates that when the last bit of a serial character was
transmitted, TDR did not contain new transmit data, so transmission has ended. TEND is a
read-only bit and cannot be written.
Bit 2: TEND Description
0 Transmission is in progress
TEND is cleared to 0 when:
•
•
1 End of transmission
TEND is set to 1 when:
•
•
•
• Bit 1 (Multiprocessor Bit (MPB)): MPB stores the value of the multiprocessor bit in receive
data when a multiprocessor format is selected for receiving in asynchronous mode. The MPB
is a read-only bit and cannot be written.
Bit 1: MPB Description
0 Multiprocessor bit value in receive data is 0
If RE is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
1 Multiprocessor bit value in receive data is 1
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The chip is reset or enters standby mode
Software reads PER after it has been set to 1, then writes 0 in PER
Software reads TDRE after it has been set to 1, then writes 0 in TDRE
The DMAC writes data in TDR
The chip is reset or enters standby mode
TE is cleared to 0 in the serial control register (SCR)
TDRE is 1 when the last bit of a one-byte serial character is transmitted
(Initial value)
(Initial value)
(Initial value)