Wait State Control Register 1 (Wcr1) Bsc - Hitachi SH7032 Hardware Manual

A.2.41 Wait State Control Register 1 (WCR1)
• Start Address: H'5FFFFA2
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: * Only write 0 in the WW1 bit when area 1 is DRAM space. When it is external memory
space, do not write 0.
Table A.42 WCR Bit Functions
Bit Bit Name Value
15–8 Read wait 0
state control
(RW7–RW0)
1
15 14
RW7 RW6 RW5
1 1
R/W R/W R/W
7 6
— —
1 1
— —
WAIT
Pin
Signal External
Input Memory Space
• Areas 1, 3–5, 7:
Not
fixed at 1 cycle
sampled
• Areas 0, 2, 6:
during
read
1 cycle + long
cycle
wait state
• Areas 1, 3–5, 7:
Sampled
wait state is 2
during
cycles plus
read
WAIT
cycle
• Areas 0, 2, 6:
(Initial
1 cycle + long
value)
wait state, or
wait state from
WAIT
13 12 11
RW4 RW3
1 1 1
R/W R/W
5 4 3
— — —
1 1 1
— — —
Number of read cycles
External Space
DRAM
Space
Column
address
cycle: Fixed
at 1 cycle
(short-pitch)
Column
address
cycle: Wait
state is 2
cycles plus
WAIT (long-
pitch) *
10 9
RW2 RW1 RW0
1 1
R/W R/W
2 1
— WW1
1 1
R/W *
—
Internal Space
Multi- On-Chip
plex On-Chip ROM,
I/O Modules RAM
Wait Fixed at Fixed at 1
state 3 cycles cycle
is 4
cycles
plus
WAIT
BSC
8
1
R/W
0
—
1
—
607