Hitachi SH7032 Hardware Manual page 447

• Bit 7 (A/D End Flag (ADF)): ADF indicates that A/D conversion is completed.
Bit 7 (ADF) Description
0 Cleared to 0 under the following conditions:
•
•
1 Set to 1 at the following times:
•
•
• Bit 6 (A/D Interrupt Enable (ADIE)): ADIE selects whether or not an A/D interrupt (ADI) is
requested when A/D conversion is completed.
Bit 6 (ADIE) Description
0 The A/D interrupt (ADI) request is disabled
1 The A/D interrupt (ADI) request is enabled
• Bit 5 (A/D Start (ADST)): ADST selects the start or halting of A/D conversion. Whenever the
A/D converter is operating, this bit is set to 1. It can also be set to 1 by the A/D conversion
trigger input pin (ADTRG).
Bit 5 (ADST) Description
0 A/D conversion is halted
•
1
•
• Bit 4 (Scan Mode (SCAN)): SCAN selects either scan mode or single mode for operation. See
section 14.4, Operation, for descriptions of these modes. The mode should be changed only
when the ADST bit is cleared to 0.
Bit 4 (SCAN) Description
0 Single mode
1 Scan mode
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The CPU reads the ADF bit while the bit is set to 1, then writes 0 in the bit
The ADI starts the DMAC and the A/D conversion register is accessed
Single mode: When A/D conversion is complete
Scan mode: When A/D conversion of all selected channels is complete
Single mode: A/D conversion is performed. This bit is automatically cleared
to 0 at the end of the conversion.
Scan mode: A/D conversion starts and continues cyclically on the selected
channels until this bit is cleared to 0 by software, a reset, or standby mode.
(Initial value)
(Initial value)
(Initial value)
(Initial value)