Registers - Hitachi SH7032 Hardware Manual

11.1.4

Registers

Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Name
Port B control register 1
Port B control register 2
Port B data register
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Next data register A
Next data register B
Notes: *1 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
*2 Bits used for TPC output cannot be written to.
*3 These addresses change depending on the TPCR settings. When TPC output groups 0
and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their
output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the
address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the
same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are
different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is
H'5FFFFF4.
312
Abbreviation R/W
PBCR1 R/W
PBCR2 R/W
R/(W) *
PBDR
TPMR R/W
TPCR R/W
NDERB R/W
NDERA R/W
NDRA R/W
NDRB R/W
Initial
Address *
Value
H'0000 H'5FFFFCC
H'0000 H'5FFFFCE
2
H'0000 H'5FFFFC2
H'F0 H'5FFFFF0
H'FF H'5FFFFF1
H'00 H'5FFFFF2
H'00 H'5FFFFF3
H'00 H'5FFFFF5/
H'5FFFFF7 *
H'00 H'5FFFFF4/
H'5FFFFF6 *
Access
1
Size
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
8, 16
3
8, 16
3