Hitachi SH7032 Hardware Manual page 526

CK
t
AD
A21–A0
HBS, LBS
CS6
AH
RD
(Read)
AD15–AD0
(Read)
DACK0
DACK1
(Read)
WRH, WRL,
WR (Write)
AD15–AD0
(Write)
DACK0
DACK1
(Write)
WAIT
Figure 20.19 Address/Data Multiplex I/O Bus Cycle
T T
1 2
t
CSD3
t t
AHD1 AHD2
t
MAD
Address
t
DACD1
t
MAD
Address
t
WTS
T
3
t t
RDD RSD
t
t
MAH
RDAC3
Data
(input)
t
DACD2
t
WSD1
t
t
WDD1
MAH
Data (output)
t
DACD3
t
WTH
T
4
t
CSD4
t
RDH
t
WSD2
t
WDH
t
DACD3
491