Hitachi SH7032 Hardware Manual page 23

4.1.1 Exception Handling Types and Priorities.............................................................. 51
4.1.2 Exception Handling Operation.............................................................................. 53
4.1.3 Exception Vector Table ........................................................................................ 54
4.2 Resets.................................................................................................................................. 56
4.2.1 Reset Types ........................................................................................................... 56
4.2.2 Power-On Reset .................................................................................................... 57
4.2.3 Manual Reset......................................................................................................... 57
4.3 Address Errors.................................................................................................................... 58
4.3.1 Address Error Sources .......................................................................................... 58
4.3.2 Address Error Exception Handling ....................................................................... 58
4.4 Interrupts ............................................................................................................................ 59
4.4.1 Interrupt Sources ................................................................................................... 59
4.4.2 Interrupt Priority Rankings.................................................................................... 59
4.4.3 Interrupt Exception Handling................................................................................ 60
4.5 Instruction Exceptions........................................................................................................ 61
4.5.1 Types of Instruction Exceptions............................................................................ 61
4.5.2 Trap Instruction ..................................................................................................... 61
4.5.3 Illegal Slot Instruction ........................................................................................... 62
4.5.4 General Illegal Instructions ................................................................................... 62
4.6 Cases in which Exceptions are Not Accepted .................................................................... 63
4.6.1 Immediately after Delayed Branch Instruction ..................................................... 63
4.6.2 Immediately after Interrupt-Disabling Instruction ................................................ 63
4.7 Stack Status after Exception Handling ............................................................................... 64
4.8 Notes................................................................................................................................... 65
4.8.1 Value of the Stack Pointer (SP) ............................................................................ 65
4.8.2 Value of the Vector Base Register (VBR) ............................................................ 65
4.8.3 Address Errors Caused by Stacking During Address Error
Exception Handling............................................................................................... 65
Section 5 Interrupt Controller (INTC)
5.1 Overview ............................................................................................................................ 67
5.1.1 Features ................................................................................................................. 67
5.1.2 Block Diagram ...................................................................................................... 67
5.1.3 Pin Configuration .................................................................................................. 69
5.1.4 Registers................................................................................................................ 69
5.2 Interrupt Sources ................................................................................................................ 70
5.2.1 NMI Interrupts ...................................................................................................... 70
5.2.2 User Break Interrupt.............................................................................................. 70
5.2.3 IRQ Interrupts ....................................................................................................... 70
5.2.4 On-Chip Interrupts ................................................................................................ 71
5.2.5 Interrupt Exception Vectors and Priority Rankings .............................................. 71
5.3 Register Descriptions.......................................................................................................... 74
5.3.1 Interrupt Priority Registers A-E (IPRA-IPRE).................................................... 74
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