Hitachi SH7032 Hardware Manual page 293

TCNT value
GRB
GRA
TIOCB
TIOCA
• Compare match output timing
The compare match signal is generated in the last state in which TCNT and the general register
match (when TCNT changes from the matching value to the next value). When a compare
match signal is generated, the output value set in TIOR is output to the output compare pin
(TIOCA, TIOCB). Accordingly, when TCNT matches a general register, the compare match
signal is not generated until the next counter clock pulse. Figure 10.22 shows the output timing
of the compare match signal.
CK
TCNT input
clock
TCNT
GR
Compare
match signal
TIOCA
TIOCB
258
Counter cleared at
GRB compare match
Figure 10.21 Example of Toggle Output
N
N
Figure 10.22 Compare Match Signal Output Timing
N – 1
Time
Toggle
output
Toggle
output