Hitachi SH7032 Hardware Manual page 226

source of the transfer request does not have to be the data transfer source or destination. When
RXI is set as the transfer request, however, the transfer source must be the SCI's receive data
register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the
SCI's transmit data register (TDR). If the transfer request is from the A/D converter, the data
transfer source must be an A/D converter register.
Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits
RS RS RS RS
3 2 1 0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 1
SCI0, SCI1: Serial communication interface channels 0 and 1
ITU0-ITU3: Channels 0–3 of the 16-bit integrated timer pulse unit
RDR0, RDR1: Receive data registers 0, 1 of SCI
TDR0, TDR1: Transmit data registers 0, 1 of SCI
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting
module (excluding DMAC)
DMA
Transfer
Request DMA Transfer Request
Source Signal
SCI0 RXI0 (SCI0 receive data full
receiver interrupt transfer request)
SCI0 TXI0 (SCI0 transmit data
transmitter empty interrupt transfer
request)
SCI1 RXI1 (SCI1 receive data full
receiver interrupt transfer request)
SCI1 TXI1 (SCI1 transmit data
transmitter empty interrupt transfer
request)
ITU0 IMIA0 (ITU0 input capture A/
compare match A)
ITU1 IMIA1 (ITU1 input capture A/
compare match A)
ITU2 IMIA2 (ITU2 input capture A/
compare match A)
ITU3 IMIA3 (ITU3 input capture A/
compare match A)
A/D ADI (A/D conversion end
converter interrupt)
Desti-
Source nation Bus Mode
Any *
RDR0 Cycle steal
Any TDR0 Cycle steal
Any *
RDR1 Cycle steal
Any *
TDR1 Cycle steal
Any * Any *
Burst/Cycle
steal
Any * Any *
Burst/Cycle
steal
Any * Any *
Burst/Cycle
steal
Any * Any *
Burst/Cycle
steal
ADDR Any Burst/Cycle
steal
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