Hitachi SH7032 Hardware Manual page 679

Table A.77 Register Status in Reset and Power-Down States (cont)
Category
16-bit integrated timer pulse TSTR
unit (ITU)
Programmable timing
pattern controller (TPC)
Watchdog timer (WDT)
Serial communication
interface (SCI)
Notes: *1 Bits 7–5 (OVF, WT/IT, TME) are initialized, bits 2–0 (CKS2–CKS0) are held.
*2 Not initialized in the case of a reset by the WDT.
644
Abbreviation Power On
Initialized
TSNC
TMDA, TMDB
TCNT0–TCNT4
GRA0–GRA4,
GRB0–GRB4
BRA3, BRA4.
BRB3, BRB4
TCR0–TCR4
TIOR0–TIOR4
TIER0–TIER4
TSR0–TSR4
TPMR Initialized
TPCR
NDERA,NDERB
NDRA, NDRB
TCNT Initialized
TCSR
2
RSTCR *
SMR Initialized
BRR
SCR
TDR
TSR
SSR
RDR
RSR
Reset State
Manual
Initialized
Initialized
Initialized
Initialized
Power-Down State
Standby Sleep
Initialized Held
Held Held
Held Held
1
*
Initialized
Initialized Held
Held
Initialized
Held