Hitachi SH7032 Hardware Manual page 108

Table 5.3 Interrupt Exception Vectors and Rankings (cont)
Interrupt Pri-
ority Order
Interrupt Source (Initial Value)
ITU3 IMIA3 0–15 (0)
IMIB3
OVI3
Reserved
ITU4 IMIA4 0–15 (0)
IMIB4
OVI4
Reserved
SCI0 ERI0 0–15 (0)
RxI0
TxI0
TEI0
SCI1 ERI1 0–15 (0)
RxI1
TxI1
TEI1
1
PRT *
PEI 0–15 (0)
A/D ITI
Reserved
Reserved
WDT ITI 0–15 (0)
2
REF *
CMI
Reserved
Reserved
Reserved —
Notes: *1 PRT: Parity control unit of bus state controller.
*2 REF: DRAM refresh control unit of bus state controller.
Priority
IPR (Bit Within
Numbers) Module
IPRD (11–8) 3
2
1
0
IPRD (7–4) 3
2
1
0
IPRD (3–0) 3
2
1
0
I PRE ( 15–12) 3
2
1
0
IPRE (11–8) 3
2
1
0
IPRE (7–4) 3
2
1
0
— —
Vec-
tor Address Offset in
No. Vector Table
92 H'00000170–H'00000173
93 H'00000174–H'00000177
94 H'00000178–H'0000017B
95 H'0000017C–H'0000017F
96 H'00000180–H'00000183
97 H'00000184–H'00000187
98 H'00000188–H'0000018B
99 H'0000018C–H'0000018F
100 H'00000190–H'00000193
101 H'00000194–H'00000197
102 H'00000198–H'0000019B
103 H'0000019C–H'0000019F
104 H'000001A0–H'000001A3
105 H'000001A4–H'000001A7
106 H'000001A8–H'000001AB
107 H' 000001AC–H' 000001AF
108 H'000001B0–H'000001B3
109 H'000001B4–H'000001B7
110 H'000001B8–H'000001BB
111 H'000001BC–H'000001BF
112 H'000001C0–H'000001C3
113 H'000001C4–H'000001C7
114 H' 000001C8–H' 000001CB
115 H' 000001CC–H' 000001CF
116 H' 000001D0–H' 000001D3
to t o
255 H' 000003FC–H' 000003FF Low
Default
Priority
Order
73