Hitachi SH7032 Hardware Manual page 427

Superh risc engine
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Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.
Start
1
bit
Serial
0
data
MPB
MPIE
RDRF
RDR
value
RXI request,
(multiprocessor
interrupt) MPIE = 0
Figure 13.13 Example of SCI Receive Operation (Own ID Does Not Match Data) (8-Bit
392
Data ID1
MPB
D
D
D
1
0
1
7
RXI interrupt
handler reads data
in RDR and clears
RDRF to 0
Data with Multiprocessor Bit and One Stop Bit)
Stop
Start
Data 1
bit
bit
1
0
D
D
0
1
Not own ID,
so MPIE is
set to 1 again
Stop
1
MPB
bit
Idle (mark)
D
0
1
7
state
ID1
No RXI
interrupt,
RDR maintains
state

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