Contention Between Gr Write And Compare Match - Hitachi SH7032 Hardware Manual

10.6.4

Contention between GR Write and Compare Match

If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes
priority and the compare match signal is inhibited. The timing is shown in figure 10.61.
write signal
Compare
match signal
Figure 10.61 Contention between General Register Write and Compare Match
T1
CK
Address
Internal
TCNT
GR
GR write cycle
T2 T3
GR address
N
N
GR write data
N + 1
M
Inhibited
293