Number Of Bus Cycle States And Dreq Pin Sample Timing - Hitachi SH7032 Hardware Manual

Bus Mode and Channel Priority Order: When a given channel (1) is transferring in burst mode
and there is a transfer request to a channel (2) with a higher priority, the transfer of the channel
with higher priority (2) will begin immediately. When channel 2 is also operating in burst mode,
the channel 1 transfer will continue when the channel 2 transfer has completely finished. When
channel 2 is in cycle-steal mode, channel 1 will begin operating again after channel 2 completes
the transfer of one transfer unit, but the bus will then switch between the two in the order channel
1, channel 2, channel 1, channel 2. Since channel 1 is in burst mode, it will not give the bus to the
CPU. This example is illustrated in figure 9.12.
Bus
CPU
status
CPU
Priority order is ch0 > ch3 > ch2 > ch1 (ch1 is in burst mode and ch2 is in cycle-steal mode).
Figure 9.12 Bus Handling when Multiple Channels are Operating

Number of Bus Cycle States and DREQ Pin Sample Timing

9.3.5
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller just as it is when the CPU is the bus master.
The bus cycle in dual address mode is controlled by wait state control register 1 (WCR1) while the
single address mode bus cycle is controlled by wait state control register 2 (WCR2). For details,
see section 8.9, Wait State Control.
DREQ Pin Sampling Timing: Normally, when DREQ input is detected immediately prior to the
rise edge of the clock pulse (CK) in external request mode, a DMAC bus cycle will be generated
and the DMA transfer performed two states later at the earliest. The sampling timing after DREQ
input detection differs by bus mode, address mode, and method of DREQ input detection.
204
DMAC DMAC DMAC
ch1 ch1 ch2
ch2
DMAC ch1
Burst mode
DMAC DMAC
ch1 ch2
ch1 ch2
DMAC ch1 and ch2
Cycle-steal mode
DMAC DMAC CPU
ch1 ch1
DMAC ch1
Burst mode
CPU