Hitachi SH7032 Hardware Manual page 599

Superh risc engine

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16-bit Access Space (In Principle, 8-Bit, 16-Bit and 32-bit Accessible) (cont)

H'5FFFFEE CASCR

H'5FFFFF0 TPMR

H'5FFFFF1 TPCR

H'5FFFFF2 NDERB

H'5FFFFF3 NDERA

H'5FFFFF4 NDRB *

H'5FFFFF5 NDRA *

H'5FFFFF6 NDRB *

H'5FFFFF7 NDRA *

H'5FFFFF8– —

Notes *1 Only 8-bit accessible. 16-bit and 32-bit access disabled.

*2 Register shared by all channels.

*3 Address for read. For writing, the addresses are H'5FFFFB8 for TCR and TCNT and

H'5FFFFBA for RSTCSR. For more information, see section 12, Watchdog Timer

(WDT), particularly section 12.2.4, Notes on Register Access.

*4 When the output triggers for TPC output group 0 and TPC output group 1 set by TPCR

are the same, the NDRA address is H'5FFFFF5; when the output triggers are different,

the NDRA address for group 0 is H'5FFFFF7 and the NDRA address for group 1 is

H'5FFFFF5. Likewise, when the output triggers for TPC output group 2 and TPC output

group 3 set by TPCR are the same, the NDRB address is H'5FFFFF4; when the output

triggers are different, the NDRB address for group 2 is H'5FFFFF6 and the NDRB

address for group 3 is H'5FFFFF4.

*5 16-bit and 32-bit accessible. 8-bit access disabled.

NDR15 NDR14 NDR13 NDR12 —

NDR11 NDR10NDR9 NDR8

NDR3 NDR2 NDR1 NDR0

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