Hitachi SH7032 Hardware Manual page 529

Table 20.7 Bus Timing (2) (cont)
Conditions: V = 3.0 to 5.5 V, AV
CC
AV , V
CC
Note: * Regular-specification products; for wide-temperature-range products, Ta = –40 to +85°C
Item
Wait setup time
Wait hold time
Read data access time 1 *
Read data access time 2 *
RAS delay time 1
RAS delay time 2
CAS delay time 1
5
CAS delay time 2 *
5
CAS delay time 3 *
Column address setup time
35% duty *
Read data
access time from
50% duty
CAS 1 * 4
Read data access time from
CAS 2 * 4
Read data access time from
RAS 1 * 4
Read data access time from
RAS 2 * 4
High-speed page mode CAS
precharge time
AH delay time 1
AH delay time 2
Multiplexed address delay
time
Multiplexed address hold
time
494
= 3.0 to 5.5 V, AV
CC
= 0 V, φ = 12.5 MHz, Ta = –20 to +75°C *
= AV
SS SS
Symbol Min
t 40
WTS
t 10
WTH
4
t t
ACC1 cyc
4
t t
ACC2 cyc
t —
RASD1
t —
RASD2
t —
CASD1
t —
CASD2
t —
CASD3
t 0
ASC
1
t t
CAC1 cyc
t
cyc
t t
CAC2 cyc
t t
RAC1 cyc
t t
RAC2 cyc
t t
CP cyc
t —
AHD1
t —
AHD2
t —
MAD
t –10
MAH
= V
CC
Max
—
—
– 44 —
× (n+2) – 44 *
2
—
40
40
40
40
40
—
× 0.65 – 35
—
× 0.5 – 35
—
× (n+1) – 35 *
2
—
× 1.5 – 35
—
× (n+2.5) – 35 *
2
—
× 0.25
—
40
40
40
—
±10%, AV = 3.0 V to
CC ref
Unit Figures
ns 20.23, 20.28, 20.32
ns
ns 20.21, 20.24, 20.25
ns 20.22, 20.23,
20.26–20.28
ns 20.24–20.27, 20.29–
20.31
ns
ns 20.24
ns 20.26, 20.27, 20.29–
20.31
ns
ns 20.24, 20.25
ns
ns
ns 20.26–20.28
ns 20.24, 20.25
ns 20.26–20.28
ns 20.25
ns 20.32
ns
ns
ns