Hitachi SH7032 Hardware Manual page 423

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in SCR is set to 1, the SCI
requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11):
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits are output, LSB first.
c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
d. Stop bit: one or two 1-bits (stop bits) are output.
e. Mark state: output of 1-bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output
of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a
transmit-end interrupt (TEI) is requested at this time.
Start
1
bit
Serial
0
data
TDRE
TEND
TXI TXI interrupt
request handler writes
data in TDR and
clears TDRE to 0
Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-Bit Data with
388
Multi-
processor
Data
bit
D D D 0/1
0 1 7
request
1 frame
Multiprocessor Bit and One Stop Bit)
Stop
Start
bit
bit
1 0 D D
0 1
TXI
Multi-
Stop
processor
Data
bit bit
Idle (mark)
D 0/1 1
7
TEI
request
1
state