General Registers A0-4 (Gra0-Gra4) Itu - Hitachi SH7032 Hardware Manual

A.2.19 General Registers A0–4 (GRA0–GRA4)
• Start Address: H'5FFFF0A (channel 0), H'5FFFF14 (channel 1), H'5FFFF1E (channel 2),
H'5FFFF28 (channel 3), H'5FFFF38 (channel 4)
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.20 GRA0–GRA4 Bit Functions
Bit Bit name
15–0 Registers used for both output
compare and input capture
15 14 13
1 1
R/W R/W R/W
7 6
1 1
R/W R/W R/W
Description
Output compare register: Set with compare match
output
Input capture register: Stores the TCNT value when the
input capture signal is generated
12 11
1 1 1
R/W R/W
5 4 3
1 1 1
R/W R/W
10 9
1 1
R/W R/W R/W
2 1
1 1
R/W R/W R/W
ITU
8
1
0
1
583