Next Data Enable Register A (Ndera) Tpc; Next Data Enable Register B (Nderb) Tpc - Hitachi SH7032 Hardware Manual

A.2.66 Next Data Enable Register A (NDERA)
• Start Address: H'5FFFFF3
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Table A.67 NDERA Bit Functions
Bit Bit Name
7–0 Next data enable 7–0
(NDER7–NDER0)
A.2.67 Next Data Enable Register B (NDERB)
• Start Address: H'5FFFFF2
• Bus Width: 8/16
Register Overview:
Bit:
Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value:
R/W:
Table A.68 NDERB Bit Functions
Bit Bit Name
7–0 Next data enable 7–0
(NDER15–NDER8)
638
7 6
NDER7 NDER6 NDER5
0 0
R/W R/W
Value
0
1
7 6
0 0
R/W R/W
Value Description
0 TPC output TP15–TP8 disabled
(Transfer from NDR15–NDR8 to PB15–PB8 disabled)
1 TPC output TP15–TP8 enabled
(Transfer from NDR15–NDR8 to PB15–PB8 enabled)
5 4
NDER4 NDER3
0 0
R/W R/W R/W
Description
Disable TPC output TP7–TP0 disabled (Initial value)
(Transfer from NDR7–NDR0 to PB7–PB0 disabled)
TPC output TP7–TP0 enabled
(Transfer from NDR7–NDR0 to PB7–PB0 enabled)
5 4
0 0
R/W R/W R/W
3 2 1
NDER2 NDER1 NDER0
0 0 0
R/W R/W
3 2 1
0 0 0
R/W R/W
TPC
0
0
R/W
TPC
0
0
R/W
(Initial value)