Timer Function Control Register (Tfcr) Itu - Hitachi SH7032 Hardware Manual

A.2.13 Timer Function Control Register (TFCR)
• Start Address: H'5FFFF03
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.14 TFCR Bit Functions
Bit Bit name
5,4 Combination modes 1, 0
(CMD1, CMD0)
3 Buffer mode B4 (BFB4)
2 Buffer mode A4 (BFA4)
1 Buffer mode B3 (BFB3)
0 Buffer mode A3 (BFA3)
7 6 5
— — CMD1
* 1 0
— — R/W
Value
0 0
0 1
1 0
1 1
0
1
0
1
0
1
0
1
4 3
CMD0 BFB4
0 0
R/W R/W
Description
Channel 3 and 4 operate normally
Channel 3 and 4 operate normally
Channels 3 and 4 are combined to operate in
complementary PWM mode
Channels 3 and 4 are combined to operate in
reset-synchronized PWM mode
GRB4 operates normally
Buffer operation of GRB4 and BRB4
GRA4 operates normally
Buffer operation of GRA4 and BRA4
GRB3 operates normally
Buffer operation of GRB3 and BRB3
GRA3 operates normally
Buffer operation of GRA3 and BRA3
2 1
BFA4 BFB3 BFA3
0 0
R/W R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
ITU
0
0
577