Reset Control/Status Register (Rstcsr) - Hitachi H8/3032 Series Hardware Manual

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Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (ø), for input to TCNT.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
0 0 0 ø/2
1 ø/32
1 0 ø/64
1 ø/128
1 0 0 ø/256
1 ø/512
1 0 ø/2048
1 ø/4096

10.2.3 Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit 7
WRST RSTOE
Initial value 0
2
*
Read/Write R/(W) R/W
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Notes: 1. RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
*1
register that indicates when a reset signal has been
6 5 4 3
— — —
0 1 1 1
— — —
Reserved bits
301
(Initial value)
2 1 0
— — —
1 1 1
— — —