Hitachi SH7032 Hardware Manual page 13

Section Page
12.2.2 Timer 338
Control/Status
Register (TCSR)
13.2.6 Serial Control 359
Register
13.2.8 Bit Rate 367
Register (BRR)
Table 13.3 Bit Rates
and BRR Settings in
Asynchronous Mode
Table 13.4 Bit
368
Rates and BRR
Settings in
Synchronous Mode
15.2 Register 427
Configuration
Table 15.2 Pin
Function Controller
Registers
16.2.1 Register 442
Configuration
Table 16.1 Port A
Register
16.3.1 Register 443
Configuration
Table 16.3 Port B
Register
16.4.1 Register 445
Configuration
Table 16.5 Port C
Register
Description
Note added
Note: * Only 0 can be written, to clear the flag.
Initial value added
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined) *
Internal clock, SCK pin used for serial clock output *
Note added
Note: Settings with an error of 1% or less are recommended.
Note deleted
Note added
Name Abbreviation R/W
Port A I/O register PAIOR
Port A control register 1 PACR1
Port A control register 2 PACR2
Port B I/O register PBIOR
Port B control register 1 PBCR1
Port B control register 2 PBCR2
Column address strobe CASCR
pin control register
Note: Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
*
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
Name Abbreviation
Port A data register PADR
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
Name Abbreviation
Port B data register PBDR
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Note added
Name Abbreviation
Port C data register PCDR
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
(Initial value)
(Initial value)
Initial Value Address*
R/W H'0000 H'5FFFFC4
R/W H'3302 H'5FFFFC8
R/W H'FF95 H'5FFFFCA
R/W H'0000 H'5FFFFC6
R/W H'0000 H'5FFFFCC
R/W H'0000 H'5FFFFCE
R/W H'5FFF H'5FFFFEE
R/W Initial Value Address*
R/W H'0000 H'5FFFFC0
R/W Initial Value Address*
R/W H'0000 H'5FFFFC2
R/W Initial Value Address*
—
R/W H'5FFFFD0
Edition
6
6
2
2
6
6
6
Access Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
6
Access Size
8, 16, 32
6
Access Size
8, 16, 32
6
Access Size
8, 16, 32