Hitachi SH7032 Hardware Manual page 237

• Burst Mode
Once the bus is obtained, the transfer is performed continuously until the transfer end condition
is satisfied. In external request mode with low-level detection at the DREQ pin, however, when
the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the
DMAC that currently has an acknowledged request ends, even if the transfer end conditions
have not been satisfied.
Burst mode cannot be used when the serial communication interface (SCI) is the transfer
request source. Figure 9.11 shows an example of DMA transfer timing in burst mode. The
transfer conditions shown in the figure are:
 Single address mode
 DREQ level detection
DREQ
Bus cycle
CPU
Figure 9.11 Transfer Example in Burst Mode (Single Address Mode, DREQ Level
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6
shows the relationship between request modes and bus modes by DMA transfer category.
202
CPU CPU DMAC DMAC DMAC DMAC DMAC
Detection)
DMAC CPU