Usage Notes On Parity Data Pins Dph And Dpl; Maximum Number Of States From Breq Input To Bus Release - Hitachi SH7032 Hardware Manual

8.11.2

Usage Notes on Parity Data Pins DPH and DPL

The following specifies the setup time, t
the CAS signal when parity data DPH and DPL are written to DRAM in long-pitch mode (early
write).
Table 8.13 Setup Time of Parity Data DPH and DPL
Item
Data setup time with respect to CAS
(for only DPH and DPL in long-pitch mode)
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the
WRH and WRL signals of this chip and used delayed writing. Normal data is also delay-written,
but this is not a problem.
RAS
SuperH
Micro- CAS
computer
RD
WRH or WRL
CK
Notes: *1 To prevent signal racing
*2 Negative edge latch

Maximum Number of States from BREQ Input to Bus Release

8.11.3
The maximum number of states from BREQ input to bus release is:
Maximum number of states for which bus is not released + approx. 4.5 states
Note: Breakdown of approx. 4.5 states:
1.5 states:
1 state (min.):
1 state (max.):
1 state:
BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the
bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43.
172
, of parity data DPH and DPL with respect to the fall of
DS
*1 *1
D
*2
Figure 8.42 Delayed-Write Control Circuit
Until BACK output after end of bus cycle
tBACD1
tBRQS
Sampling in 1 state before end of bus cycle
Symbol
t
DS
DWRH or DWRL
Q
Q
Min
-5ns
RAS
DRAM
CAS
OE
WE