Hitachi SH7032 Hardware Manual page 607

Table A.9 ADCSR Bit Functions
Bit Bit name
7 A/D end flag (ADF)
6 A/D interrupt enable
(ADF)
5 A/D start (ADST)
4 Scan mode (SCAN)
3 Clock select (CKS)
2–0 Channel select 2–0
572
Value Description
0 Clear conditions: (1) 0 written in ADF after reading ADF =
1; (2) DMAC started by ADI interrupt and A/D converter
register is accessed
1 Set Conditions: (1) Single mode: A/D conversion ends;
(2) Scan mode: A/D conversion of all channels set has
ended
0 Interrupt requested by A/D conversion (ADI) disabled
1 Interrupt requested by A/D conversion (ADI) enabled
0 Disable A/D conversion
1 (1) Single mode: Start A/D conversion and when
conversion ends, automatically cleared to zero; (2) Scan
mode: Start A/D conversion and sequentially continue
converting the selected channels until cleared to 0 by
software, reset, or standby mode
0 Single mode
1 Scan mode
0 Conversion time = 236 cycles (max)
1 Conversion time = 134 cycles (max)
CH2 CH1 CH0 Single mode
0 0 0
1
1 0
1
1 0 0
1
1 0
1
AN0 (Initial value)
AN1
AN2
AN3
AN4
AN5
AN6
AN7
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Scan mode
AN0 (Initial value)
AN0, AN1
AN0–AN2
AN0–AN3
AN4
AN4, AN5
AN4–AN6
AN4–AN7