Hitachi SH7032 Hardware Manual page 415

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that
the transmit data register (TDR) contains new data, and loads this data from TDR into the
transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCR, the SCI
requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
1. Start bit: one 0 bit is output.
2. Transmit data: seven or eight bits of data are output, LSB first.
3. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is
output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
4. Stop bit: one or two 1-bits (stop bits) are output.
5. Mark state: output of 1-bits continues until the start bit of the next transmit data.
6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then
continues output of 1-bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested.
Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
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