Buffer Registers A3, 4 (Bra3, Bra4) Itu - Hitachi SH7032 Hardware Manual

A.2.21 Buffer Registers A3, 4 (BRA3, BRA4)
• Start Address: H'5FFFF2C (channel 3), H'5FFFF3C (channel 4)
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.22 BRA3, BRA4 Bit Functions
Bit Bit name
15–0 Buffer registers used for output
compare/input capture
15 14 13
1 1
R/W R/W R/W
7 6
1 1
R/W R/W R/W
12 11
1 1 1
R/W R/W
5 4 3
1 1 1
R/W R/W
Description
Output compare register: Transfers to GRA the
value stored up to compare match generation
Input capture register: Stores the value stored in
GRA up to input capture signal generation
10 9
1 1
R/W R/W R/W
2 1
1 1
R/W R/W R/W
ITU
8
1
0
1
585