Serial Status Register - Hitachi SH7032 Hardware Manual

Bit 1: Bit 0:
Description *
CKE1 CKE0
0 0 Asynchronous mode
Synchronous mode
0 1 Asynchronous mode
Synchronous mode
1 0 Asynchronous mode
Synchronous mode
1 1 Asynchronous mode
Synchronous mode
Notes: *1 The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to
select the SCK function and SCK input/output for the SCK pin.
*2 Initial value
*3 The output clock frequency is the same as the bit rate.
*4 The input clock frequency is 16 times the bit rate.
13.2.7

Serial Status Register

The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate the SCI operating status.
The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is
initialized to H'84 by a reset and in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written, to clear the flag.
• Bit 7 (Transmit Data Register Empty (TDRE)): TDRE indicates that the SCI has loaded
transmit data from TDR into TSR and new serial transmit data can be written in TDR.
1
7 6
TDRE RDRF ORER
1 0
R/(W)* R/(W)* R/(W)*
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined) *
Internal clock, SCK pin used for serial clock output *
Internal clock, SCK pin used for clock output *
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input *
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input *
External clock, SCK pin used for serial clock input
5 4 3
FER PER
0 0 0
R/(W)* R/(W)*
(Initial value)
(Initial value)
3
4
4
2 1
TEND MPB MPBT
1 0
R R R/W
2
2
0
0
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