Hitachi SH7032 Hardware Manual page 290

Superh risc engine

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• TCNT counter timing

Internal clock source: Bits TPSC2–TPSC0 in TCR select the system clock (CK) or one of three

internal clock sources (φ/2, φ/4, φ/8) obtained by prescaling the system clock. Figure 10.17

shows the timing.

External clock source: The external clock input pin (TCLKA–TCLKD) source is selected by

bits TPSC2–TPSC0 in TCR and its valid edges are selected with the CKEG1 and CKEG0 bits

in TCR. The rising edge, falling edge, or both edges can be selected. The pulse width of the

external clock signal must be at least 1.5 system clocks when a single edge is selected and at

least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted

correctly. Figure 10.18 shows the timing when both edges are detected.

Figure 10.15 Free-Running Counter Operation

Figure 10.16 Periodic Counter Operation

Counter cleared by

GR compare match

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