Pin Configuration - Hitachi SH7032 Hardware Manual

8.1.3

Pin Configuration

Table 8.1 shows the BSC pin configuration.
Table 8.1 Pin Configuration
Name
Chip select 7–0
Read
High write
Low write
Write
High byte strobe
Low byte strobe
Row address strobe RAS
High column
address strobe
Low column
address strobe
Address hold
Wait
Address bus
Data bus
Data bus parity high DPH
Data bus parity low
Notes: *1 Doubles with the WRL pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
Control Register (BCR), for details.)
*2 Doubles with the A0 pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
Control Register (BCR), for details.)
*3 Doubles with the WRH pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
Control Register (BCR), for details.)
Abbreviation I/O
CS7–CS0
O
RD
O
WRH
O
WRL
O
WR *
1
O
HBS *
2
O
LBS *
3
O
O
CASH
O
CASL
O
AH
O
WAIT
I
A21–A0 O
AD15–AD0 I/O
I/O
DPL I/O
Function
Chip select signal that indicates the area being
accessed
Strobe signal that indicates the read cycle
Strobe signal that indicates write cycle to upper 8
bits
Strobe signal that indicates write cycle to lower 8
bits
Strobe signal that indicates write cycle
Strobe signal that indicates access to upper 8 bits
Strobe signal that indicates access to lower 8 bits
DRAM row address strobe signal
Column address strobe signal for accessing the
upper 8 bits of the DRAM
Column address strobe signal for accessing the
lower 8 bits of the DRAM
Signal for holding the address for address/data
multiplexing
Wait state request signal
Address output
Data I/O. During address/data multiplexing,
address output and data input/output
Parity data I/O for upper byte
Parity data I/O for lower byte
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