Appendix B Pin States - Hitachi SH7032 Hardware Manual

Table B.1 Pin State In Resets, Power-Down State, and Bus-Released State
Category
Clock
System control
Interrupt
Address bus
Data bus
Bus control
Direct memory access DREQ0,DREQ1
controller (DMAC)
16-bit integrated timer TIOCA0–TIOCA4
pulse unit (ITU)
Timing pattern
controller (TPC)
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Appendix B Pin States

Pin Power-On
CK O
RES
I
WDTOVF
H
BREQ
—
BACK
Z
NMI I
IRQ7–IRQ0
—
IRQOUT
—
A21–A0 H
AD15–AD0 Z
DPH,DPL —
WAIT
I
CS7
—
CS6–CS0
Z
RD
H
WRH (LBS),WRL
H
(WR)
RAS
—
CASH,CASL
—
AH
—
—
DACK0,DACK1 Z
—
TIOCB0–TIOCB4 —
TOCXA4, —
TOCXB4
TCLKA–TCLKD —
TP15–TP0 —
Pin State
Reset Power-Down
Manual Standby Sleep Released
1
H *
O
I I
1
H *
H
I Z
O Z
I I
I Z
1
O *
O
O Z
Z Z
Z Z
I * 2
Z
O Z
O Z
O Z
O Z
1
O *
O
O O
O Z
I Z
1
K *
O
1
K *
I
1
K *
I
1
K *
I
I Z
1
K *
I
Bus
O O
I I
O O
I I
O L
I I
I I
H O
H Z
Z Z
Z Z
I * 2 I * 2
H Z
H Z
H Z
H Z
O Z
O Z
H Z
I I
O O
I/O I/O
I/O I/O
O O
I I
O O