On-Chip Interrupts; Interrupt Exception Vectors And Priority Rankings - Hitachi SH7032 Hardware Manual

5.2.4

On-Chip Interrupts

On-chip interrupts are interrupts generated by the following 6 on-chip supporting modules:
• Direct memory access controller (DMAC)
• 16-bit integrated timer pulse unit (ITU)
• Serial communication interface (SCI)
• Bus state controller (BSC)
• A/D converter (A/D)
• Watchdog timer (WDT)
A different interrupt vector is assigned to each interrupt source, so the exception handling routine
does not have to decide which interrupt has occurred. Priority levels 0–15 can be assigned to
individual on-chip supporting module in interrupt priority registers C–E (IPRC–IPRE). On-chip
interrupt exception handling sets the interrupt mask level bits (I3–I0) in the status register (SR) to
the priority level value of the on-chip interrupt that was accepted.
5.2.5

Interrupt Exception Vectors and Priority Rankings

Table 5.3 lists the vector numbers, vector table address offsets, and interrupt priority order of the
interrupt sources.
Each interrupt source is allocated a different vector number and vector table address offset. The
vector table address is calculated from this vector number and address offset. In interrupt
exception handling, the exception handling routine start address is fetched from the vector table
indicated by this vector table address. See table 4.3, Calculation of Exception Vector Table
Address, in section 4, Exception Handling, for details on this calculation.
Arbitrary interrupt priority levels between 0 and 15 can be assigned to IRQ and on-chip supporting
module interrupt sources by setting interrupt priority registers A–E (IPRA–IPRE) for each pin or
module. The interrupt sources for IPRC–IPRE, however, must be ranked in the order listed under
Priority Within Module in table 5.3 and cannot be changed. A reset assigns priority level 0 to IRQ
and on-chip supporting module interrupts. If the same priority level is assigned to two or more
interrupt sources, and interrupts from those sources occur simultaneously, their priority order is
the default priority order indicated at the right in table 5.3.
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