Timer I/O Control Registers 0-4 (Tior0-Tior4) Itu - Hitachi SH7032 Hardware Manual

A.2.15 Timer I/O Control Registers 0–4 (TIOR0–TIOR4)
• Start Address: H'5FFFF05 (channel 0), H'5FFFF0F (channel 1), H'5FFFF19 (channel 2),
H'5FFFF23 (channel 3), H'5FFFF33 (channel 4)
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.16 TIO0–TIO4 Bit Functions
Bit Bit name
6–4 I/O control B2–0
(IOB2–IOB0)
2–0 I/O control A2–0
(IOA2–IOA0)
Note: * 0 or 1
7 6 5
— IOB2 IOB1
0 0
*
— R/W R/W
Value Description
0 0 0 GRB is output
compare register
0 0 1
0 1 0
0 1 1
1 0 0 GRB is input
1 capture register
1 0
1 1
*
0 0 0 GRA is output
compare register
0 0 1
0 1 0
0 1 1
1 0 0 GRA is input
1 capture register
1 0
1 1 *
4 3
IOB0 — IOA2
0 1
R/W — R/W
Pin output due to compare match
disabled
0 output on GRB compare match
1 output on GRB compare match
Toggle output on GRB compare match
(1 output on channel 2 only)
Input capture to GRB on rising edge
Input capture to GRB on falling edge
Input capture on both rising and falling
edges
Pin output due to compare match
disabled
0 output on GRA compare match
1 output on GRA compare match
Toggle output on GRA compare match
(1 output on channel 2 only)
Input capture to GRA on rising edge
Input capture to GRA on falling edge
Input capture on both rising and falling
edges
ITU
2 1 0
IOA1 IOA0
0 0 0
R/W R/W
(Initial value)
(Initial value)
579