Block Diagram - Hitachi SH7032 Hardware Manual

Superh risc engine

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• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full

interrupts can start the direct memory access controller (DMAC) to transfer data.

Block Diagram

Figure 13.1 shows a block diagram of the SCI.

RSR: Receive shift register

RDR: Receive data register

TSR: Transmit shift register

TDR: Transmit data register

Module data bus

receive control

Parity check

SMR: Serial mode register

SCR: Serial control register

SSR: Serial status register

BRR: Bit rate register

Figure 13.1 Block Diagram of SCI

External clock

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