Hitachi SH7032 Hardware Manual page 166

DRAM control register (DCR) is set to 1 to use the address multiplex function, bits A23–A0 are
multiplexed and output from pins A15–A0, so a maximum 16-Mbyte space can be used. When
DRAM space is accessed, the CS1 signal is not valid and the pin function controller should be set
for access with CAS (CASH and CASL) and RAS signals.
Logical address space
H'9000000
H'1000000
H'93FFFFF
H'9400000
H'13FFFFF
H'1400000
H'97FFFFF
H'9800000
H'17FFFFF
H'1800000
H'9BFFFFF
H'9C00000
H'1BFFFFF
H'1C00000
H'9FFFFFF
H'1FFFFFF
A27 = 1:
16-bit space
DRAME = 0 or DRAME = 1, MXE = 0
Areas 2–4: Areas 2–4 are areas with address bits A26–A24 set to 010, 011, and 100, respectively,
and address ranges of H'2000000–H'2FFFFFF and H'A000000–H'AFFFFFF (area 2), H'3000000–
H'3FFFFFF and H'B000000–H'BFFFFFF (area 3), and H'4000000–H'4FFFFFF and H'C000000–
H'CFFFFFF (area 4). Figure 8.7 shows a memory map of area 2, which is representative of areas
2–4.
Shadow
Actual space
Shadow
External
memory
space
(4 Mbytes)
• Valid
Shadow
address
A21–A0
(A23 and
A22 not
output)
• CS1
Shadow
valid
A27 = 0:
8-bit space
Figure 8.6 Memory Map of Area 1
Logical address space
H'9000000
H'1000000
H'9FFFFFF
H'1FFFFFF
A27 = 1:
16-bit space
Actual space
DRAM
space
Shadow
(maximum
16 Mbytes)
• Multiplexed
A27 = 0:
(MXE = 1):
8-bit space
16-bit space
• Not multi-
plexed
(MXE = 0):
4-Mbyte
space
• CS1 not
valid (CAS,
RAS output)
DRAME = 1
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