Hitachi SH7032 Hardware Manual page 497

or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the
states of these pins, see appendix B, Pin States.
Table 19.3 Register States in Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Pin function controller (PFC)
I/O ports
Direct memory access controller
(DMAC)
Watchdog timer (WDT)
16-bit integrated timer pulse unit
(ITU)
Programmable timing pattern
controller (TPC)
Serial communication interface
(SCI)
A/D converter (A/D)
Power-down state register
462
Registers Initialized
—
—
—
—
—
All registers
• Bits 7–5 (OVF, WT/IT, TME)
in timer control status
register (TCSR)
• Reset control/status register
(RSTCSR)
All registers
—
• Receive data register (RDR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
All registers
—
Registers That Hold Data
All registers
All registers
All registers
All registers
All registers
—
• Bits 2–0 (CKS2–CKS0) in
timer control status
register (TCSR)
• Timer counter (TCNT)
—
All registers
—
—
Standby control register
(SBYCR)