Hitachi SH7032 Hardware Manual page 647

Table A.45 DCR Bit Functions
Bit Bit Name
15 2-CAS system/2-WE
system (CW2)
14 RAS down (RASD)
13 Number of RAS pre-charge
cycles (TPC)
12 Burst operation enable (BE) 0
11 CAS duty (CDTY)
10 Multiplex enable (MXE)
9,8 Multiplex shift count 1,0
(MXC1, MXC0)
612
Value Description
2-CAS system: CASH, CASL, and WRL signals are
0
valid
2-WE system: CASL, WRH, and WRL signals are
1
valid
RAS up mode: Returns RAS signal to high and waits
0
for next DRAM access
RAS down mode: Leaves RAS signal low and waits
1
for next DRAM access
0 1-cycle pre-charge cycle inserted
1 2-cycle pre-charge cycle inserted
Normal mode: Full access
1 High-speed page mode: Burst operation
CAS signal high width duty ratio is 50% (Initial value)
0
CAS signal high width duty ratio is 35%
1
0 Row address and column address not multiplexed
1 Row address and column address multiplexed
Row address shift
(MXE = 1)
0 0 8 bits (Initial value)
0 1 9 bits
1 0 10 bits
1 1 Reserved
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Row address for comparison
during burst (MXE = 0 or 1)
A27–A8 (Initial value)
A27–A9
A27–A10
Reserved