Hitachi SH7032 Hardware Manual page 212

On-chip
ROM
On-chip
RAM
On-chip
supporting
module
DREQ0, DREQ1
ITU
SCI
A/D converter
DACK0, DACK1
DEIn
External
ROM
External
RAM
External device
(memory-
mapped)
External
device (with
acknowledge)
DMAOR: DMA operation register
SARn: DMA source address register
DARn: DMA destination address register
TCRn: DMA transfer count register
CHCRn: DMA channel control register
DEIn: DMA transfer-end interrupt request to CPU
n: 0–3
Bus interface
Bus controller
Figure 9.1 Block Diagram of DMAC
DARn
Iteration
control
Register
control
CHCRn
Start-up
control
DMAOR
Request
priority
control
SARn
TCRn
DMAC
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